Santosh Kumar Gupta

Modeling of cylindrical surrounding gate MOSFETs including the fringing field effects

A physically based analytical model for surface potential and threshold voltage including the fringing gate capacitances in cylindrical surround gate (CSG) MOSFETs has been developed. Based on this a subthreshold drain current model has also been derived. This model first computes the charge induced in the drain/source region due to the fringing capacitances and considers an effective charge distribution in the cylindrically extended source/drain region for the development of a simple and compact model. The fringing gate capacitances taken into account are outer fringe capacitance, inner fringe capacitance, overlap capacitance, and sidewall capacitance. The model has been verified with the data extracted from 3D TCAD simulations of CSG MOSFETs and was found to be working satisfactorily.

Potential modeling and performance analysis of junction-less quadruple gate MOSFETs for analog and RF applications

Abstract In this paper, a quasi-3-D analytical model for Junction-less quadruple MOSFET is presented. The model is developed based on an equivalent number of gates by solving two 2-D Poissons equations instead of solving complex full 3-D Poissons equation considering it as two double gate MOSFETs. The model is verified for different channel length, height (or width), oxide thickness, doping concentration, and bias voltages. The presented device is then analysed for digital, analog and RF performance parameters using numerical computations. It has been shown in the paper that the JLQG provides improved gain and SCEs with increase of channel length and decrease in height (or width), oxide thickness and doping concentration whereas a higher cut-off frequency is obtained by decreasing channel length and increase in height (or width), oxide thickness and doping concentration. The doping affects the device performance parameters the most.

Linearity Distortion Analysis of Junctionless Quadruple Gate MOSFETs for Analog Applications

This paper examines a Junctionless quadruple gate (JLQG) MOSFET for analog and linearity distortion performance by numerically calculating transconductance and its higher order derivatives (gm1, gm2and gm3), VIP2, VIP3, IIP3 and IMD3. Influence of various physical device parameters: channel length, height (or width), gate oxide thickness, and channel doping concentration on the linearity distortion parameters are analyzed. From the numerical calculations it has been shown that the desirable characteristics for analog application at a given technology node are obtained for higher values of tSi, tox, and Nd. The present analysis also reveals the guidelines for the design of JLQG MOSFETs with least linearity distortion.

Analytical Modeling of a Triple Material Double Gate TFET with Hetero-Dielectric Gate Stack

In this paper, we propose and develop an analytical model of a Triple material double gate Tunnel Field Effect Transistor (TM-DG TFET) with hetero-dielectric gate oxide stack comprising of SiO2 and HfO2. The two-dimensional Poisson’s equation has been solved using parabolic-approximation method to model the channel potential and electric field. Analytical model of drain current is developed by integrating the band-to-band tunneling generation rate over the channel thickness (tsi) and shortest tunneling path (Lmin

Leakage reduction in ultra deep sub micron technology

L_{min }

On the analog and radio frequency performance of Junctionless Single Metal Gate cylindrical surround gate metal-oxide-semiconductor field-effect transistors

). A Transconductance model is also developed using this drain current model. The proposed TM-DG TFET also provides better result with reference to input-output characteristics, subthreshold swing, ION/IOFF current ratio and ambipolar effect compared to the dual material double gate (DM-DG) TFET. The analytical model has been validated with the numerical data obtained from commercial TCAD software.

Study of Nitrogen terminated doped zigzag GNR FET exhibiting negative differential resistance

Leakage power is a major issue of concern in Deep Sub-Micron (DSM) and Ultra Deep Sub-micron technology (UDSM) in CMOS circuit design. LECTOR-EP (LECTOR technique with extra PMOS), LECTOR-EN (LECTOR technique with extra NMOS) and Double LECTOR techniques have been proposed in this paper to reduce the leakage. Due to increase in resistance for the path from Vdd to ground, substantial reduction in leakage is obtained in comparison to CMOS circuits. Leakage performance for NAND gate with CMOS, LECTOR and proposed configurations have been performed and compared. The proposed circuits offer improved leakage performance than LECTOR technique. Simulation has been done using Synopsys HSPICE tool for 32 nm technology at 25° C and 110° C.

Threshold voltage model of junctionless cylindrical surrounding gate MOSFETs including fringing field effects

In this paper a comprehensive study of Junctionless Single Metal cylindrical surround gate (JLSM CSG) metal-oxide–semiconductor field-effect transistor (MOSFET) characteristics have been presented and compared with a conventional CSG MOSFET of identical dimensions. The variations of different analog and radio frequency performance parameters have been studied by varying the gate length, channel diameter, and metal gate workfunction using three-dimensional numerical simulations in terms of transconductance, transconductance generation factor, early voltage, unity gain cutoff frequency, maximum frequency of oscillation, etc. The JLSM CSG MOSFETs are found to exhibit superior characteristics compared to the conventional CSG MOSFETs.