Saravanan Sethuraman

Timing correlation between clock & data strobe with dynamic rank switching in DDR3 RDIMMs

Memory plays a significant role in successful operations of modern day servers. DDR3 memory has been around for a while and the next generation is almost available. There are lots of challenges which still exist and are not fully uncovered with the DDR3 based ISRDIMMs and discussed in this paper is a unique problem faced during the server memory characterization of ISRDIMMs. Issues were unearthed in timing relationship between the Clock and WR DQS in a multi-Rank DIMM and experiments were conducted to find a suitable solution. The proposed solution uses a Built-In-Self-Test engine to toggle the phase rotator attached to a particular bit to overcome the zero timing margin issues. Experiments were conducted with single and multi-Rank DIMMs, sequential & random DATA pattern and with different addressing schemes to root cause the problem and ensure the proposed solution works fine in all cases.

Vref optimization in DDR4 RDIMMs for improved timing margins

JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology. We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training. Data pattern complexity, total training time and accuracy of training are investigated and optimized. Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition. Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency. Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time. Our results show significant benefits with respect to PDA vs rank basis Vref training.

Improve timing margins on multi-rank DDR3 RDIMM using read-on die termination sequencing

Modern computer systems have large amounts of DRAM running at fast cycle times. JEDEC standards for DDR3 DRAMs set the bounds of operation, but there is significant opportunity for maximizing the operating performance and reliability by optimizing the electrical parameters and the register settings across the many DIMMs in a system. Specifically, it is essential for the system designers to maximize the setup and hold timing margins for robust system operation. In this paper the hold timing of the data bus read operation is investigated. The methodology is presented and applied to setting the On-Die Termination (ODT) start/stop delay settings for optimal operation. The settings are verified by hardware characterization that confirms the updated delay settings improve the timing margin by performing a timing schmoo and observation of the waveforms with a logic analyzer and oscilloscope.