Anil B. Lingambudi

A case study of high-speed serial interface simulation with IBIS-AMI models

High-end, high-performance computers use high-speed serial interfaces to pass data and control signals between the electronic components in the systems. These interfaces include proprietary interfaces unique to a class of systems and some interfaces, such as PCIe & SAS, which have publicly available standards and specifications that enable communication between electronic components from different manufactures. The IBIS-AMI model has been developed to facilitate circuit simulation of high-speed serial interfaces and is particularly useful in simulating communication between transmitters and receivers procured from different manufactures. The simulations are performed to ensure that the interface specifications are met, including the eye characteristics, and that the bit error rate (BER) is less than a specified maximum. There are many variables and long bit strings needed to predict a BER of sufficiently low amplitude. Therefore, an efficient and accurate estimation of BER requires significantly long simulations times. In this paper, we use the example of a 6 gigabit per second (Gb/s) SAS interface to illustrate our proposed simulation method of combining an empirical and analytical approach to estimate the effects of inter-symbol interference (ISI) and channel jitter using an IBIS-AMI models.

A case study: Power measurement and optimization of DDR3 DIMM in servers

Optimization of memory power is an important design objective in any computer device. However, servers are especially a challenge because the number of DRAMs are large and in aggregate can consume up to 40% of the overall system power. This paper presents power measurement experiments under a variety of server system conditions. Some techniques are proposed to optimize the overall power consumption. The experiments must be carefully planned with defined workloads and voltage regulators of sufficient resolution so that the measurements can be used for both analysis and prediction. The primary objective of this work is to accurately project the power demand from the hardware measurements to confirm that all system DRAM configurations stay within their power budget.

Timing correlation between clock & data strobe with dynamic rank switching in DDR3 RDIMMs

Memory plays a significant role in successful operations of modern day servers. DDR3 memory has been around for a while and the next generation is almost available. There are lots of challenges which still exist and are not fully uncovered with the DDR3 based ISRDIMMs and discussed in this paper is a unique problem faced during the server memory characterization of ISRDIMMs. Issues were unearthed in timing relationship between the Clock and WR DQS in a multi-Rank DIMM and experiments were conducted to find a suitable solution. The proposed solution uses a Built-In-Self-Test engine to toggle the phase rotator attached to a particular bit to overcome the zero timing margin issues. Experiments were conducted with single and multi-Rank DIMMs, sequential & random DATA pattern and with different addressing schemes to root cause the problem and ensure the proposed solution works fine in all cases.

Vref optimization in DDR4 RDIMMs for improved timing margins

JEDEC DDR4 SDRAM adopted the internal Data (DQ) reference voltage (VREFDQ) generation scheme as opposed to DDR3 SDRAM where VREF was generated by an external device that produced fixed (constant) voltage irrespective of the loading on the device, power supply variations, temperature changes, and the passage of time. With the introduction of Per DRAM Addressability (PDA) in DDR4 memory and the internal VREF combined, discussed in this paper is a novel approach to determine the best VREF settings for a given topology. We will use memory controller built-in-self-test (MCBIST) to get a stressed pattern in place of simple Multi Purpose Register (MPR) data pattern and will be exercised as part of post DRAM training. Data pattern complexity, total training time and accuracy of training are investigated and optimized. Initial training of the DRAM is done with the initial VREF calculated based on driver strength and On Die Termination (ODT) condition. Complexities of different VREF settings are applied on multiple ranks in the same DIMM using the PDA to maximize timing margin and power efficiency. Per-DRAM VREF training has been also performed using PDA to study tradeoff between timing margin and total training time. Our results show significant benefits with respect to PDA vs rank basis Vref training.

Algorithmic Modeling Interface Interoperability Case Study

The Algorithmic Modeling Interface (AMI) defines a standard syntax for modeling the physical layer of high-speed serial interfaces such as PCI Express (PCIe) and Serial Attach SCSI (SAS). Although it has been gathering momentum since it emerged in 2008, the models developed under this standard continue to experience basic functionality and interoperability issues. Many models only run under one simulator and require multiple revisions before they will run in another simulator. Our paper presents a case study of three different AMI models in three different simulators together with recommendations for insuring the quality of these critical elements of serial interface simulation.

Improve timing margins on multi-rank DDR3 RDIMM using read-on die termination sequencing

Modern computer systems have large amounts of DRAM running at fast cycle times. JEDEC standards for DDR3 DRAMs set the bounds of operation, but there is significant opportunity for maximizing the operating performance and reliability by optimizing the electrical parameters and the register settings across the many DIMMs in a system. Specifically, it is essential for the system designers to maximize the setup and hold timing margins for robust system operation. In this paper the hold timing of the data bus read operation is investigated. The methodology is presented and applied to setting the On-Die Termination (ODT) start/stop delay settings for optimal operation. The settings are verified by hardware characterization that confirms the updated delay settings improve the timing margin by performing a timing schmoo and observation of the waveforms with a logic analyzer and oscilloscope.

Timing margin analysis and Power measurement with DDR4 memory

DIMMs built with DDR4 (Double Data Rate 4th-generation) SDRAM (Synchronous Dynamic Random-Access Memory) are the current memory components used on HPC (High Performance Computing) systems. The DDR4 signal interfaces operate up to a 3200 Mbps data rate and at 1.2 V. This is a higher frequency at a lower voltage, therefore lower power, than the third generation DDR3 DIMMs. The higher frequency and lower voltage results in decreased timing margins. The characterization of the timing margins and power usage is of significantly increased importance in DDR4. In this paper, a methodology for experimentally quantifying timing margins and power is applied at bounding voltage and frequency corners to plan, design, and architect HPC systems optimized for power consumption and with timing margin.