Satoshi Aoyama

Phase-shift mask pattern accuracy requirements and inspection technology

Computer simulations and i-line phase shift lithography experiments with programmed 5X phase shift reticle defects were used to investigate the effect of opaque and phase-shift layer defects on sub-half-micron lines. Both the simulations and the experiments show that defects in the phase shift layer print larger than corresponding opaque defects, with 0.3-0.4 micrometers defects affecting sub-half-micron critical dimensions by more than the allowable 10%. Inspection of programmed phase shift defects with a prototype mask inspection system confirmed that the system finds the 0.3-0.4 micrometers phase shift defects critical to sub-half-micron lithography.

A 33-Megapixel 120-Frames-Per-Second 2.5-Watt CMOS Image Sensor With Column-Parallel Two-Stage Cyclic Analog-to-Digital Converters

A 33-megapixel 120-frames/s (fps) CMOS image sensor has been developed. The 7808 × 4336 pixel 2.8-μm pixel pitch CMOS image sensor with 12-bit, column-parallel, two-stage, cyclic analog-to-digital converters (ADCs) and 96 parallel low-voltage differential signaling output ports operates at a data rate of 51.2 Gb/s. The pipelined operation of the two cyclic ADCs reduces the conversion time. This ADC architecture also effectively lowers the power consumption by exploiting the amplifier function of the cyclic ADC. The CMOS image sensor implemented with 0.18-μm technology exhibits a sensitivity of 0.76 V/lx·s without a microlens and a random noise of 5.1 erms- with no column amplifier gain and 3.0erms- with a gain of 7.5 at 120 fps while dissipating only 2.45 and 2.67 W, respectively.

Column-Parallel Correlated Multiple Sampling Circuits for CMOS Image Sensors and Their Noise Reduction Effects

For low-noise complementary metal-oxide-semiconductor (CMOS) image sensors, the reduction of pixel source follower noises is becoming very important. Column-parallel high-gain readout circuits are useful for low-noise CMOS image sensors. This paper presents column-parallel high-gain signal readout circuits, correlated multiple sampling (CMS) circuits and their noise reduction effects. In the CMS, the gain of the noise cancelling is controlled by the number of samplings. It has a similar effect to that of an amplified CDS for the thermal noise but is a little more effective for 1/f and RTS noises. Two types of the CMS with simple integration and folding integration are proposed. In the folding integration, the output signal swing is suppressed by a negative feedback using a comparator and one-bit D-to-A converter. The CMS circuit using the folding integration technique allows to realize a very low-noise level while maintaining a wide dynamic range. The noise reduction effects of their circuits have been investigated with a noise analysis and an implementation of a 1Mpixel pinned photodiode CMOS image sensor. Using 16 samplings, dynamic range of 59.4 dB and noise level of 1.9 e− for the simple integration CMS and 75 dB and 2.2 e− for the folding integration CMS, respectively, are obtained.

Shielded-Loop-Type Onchip Magnetic-Field Probe to Evaluate Radiated Emission From Thin-Film Noise Suppressor

A silicon integrated RF magnetic field probe has been designed and microfabricated using CMOS-silicon-on-insulator (SOI) technology with a 0.15-mum design rule on a high-resistivity silicon substrate. The size of the coil window was 180times180 mum2. Coil and electrodes were separated by a 530-mum-long stripline so as to avoid stray voltage induction at the electrode portion. This probe was applied to evaluate the radiated emission from a thin-film electromagnetic noise suppressor. It was clarified and shown that the field intensity was suppressed by 4.0 dB at the center of the signal line at 1 GHz

Effects of Negative-Bias Operation and Optical Stress on Dark Current in CMOS Image Sensors

A negative-bias operation of the transfer gate has revealed a major origin of dark current defects of CMOS image sensors. Charge injection from the photodiode to the substrate at the negative-bias operation has been avoided by an improved well structure. A strong visible light has been observed to cause damage with an increase in the dark current under the normal operating condition, and the damage has been annealed in the power-off mode. This indicates that the strong light possibly causes a threshold voltage shift, which is explained by the photon-assisted tunneling or emission mechanisms. Multiple stress-and-anneal cycles have been found to cause an optical hardening effect, which can be explained by immobile trapped holes.

A Time-of-Flight Range Image Sensor With Background Canceling Lock-in Pixels Based on Lateral Electric Field Charge Modulation

This paper presents a CMOS time-of-flight (ToF) range image sensor using high-speed lock-in pixels with background light canceling capability. The proposed lock-in pixel uses MOS gate-induced lateral electric field control of depleted potential of pinned photodiode for implementing a multiple-tap charge modulator while achieving a high-speed charge transfer for high-time resolution. A TOF image sensor with 320 x 240 effective pixels is implemented using a 0.11-μm CMOS image sensor process. The TOF sensor has a range resolution of less than 12 mm without background light and 20 mm under background line for the range from 0.8 to 1.8 m and integration time of 50 ms. The effectiveness of in-pixel background light canceling with a three-tap output pixel is demonstrated.

A 1.7-in, 33-Mpixel, 120-frames/s CMOS Image Sensor With Depletion-Mode MOS Capacitor-Based 14-b Two-Stage Cyclic A/D Converters

A 1.7-in, 33-Mpixel, 120-frames/s, 14-bit CMOS image sensor has been developed. The 7936 (H) × 4412 (V) pixel CMOS image sensor, which uses 14-b depletion-mode MOS (DMOS) capacitor-based two-stage cyclic A/D converters (ADCs) and 64 parallel scalable low-voltage signaling output ports, operates at a data rate of 63.8 Gb/s. DMOS capacitors have a high capacitance density, but it is difficult to achieve high bit resolutions in ADCs with these capacitors because their capacitance depends on the applied voltage. Column-parallel two-stage cyclic ADCs overcome this difficulty using a split-sampling DMOS capacitors architecture. The two-stage cyclic ADC with the DMOS capacitors at a 6.4-μm column pitch exhibited a differential nonlinearity of 0.95/-0.80 least significant bit (LSB); the integral nonlinearity was 2.57/-28.27 LSB at a 14-b resolution. The CMOS image sensor implemented with a 90-/65-nm technology exhibited a sensitivity of 5.22 V/lx·s and a random noise of 3.6 e-rms with a gain of 3.3 at 120 frames/s while dissipating 3.2 W.

Novel process for phase-shifting mask fabrication

In this new process for phase-shifting mask fabrication, molybdenum silicide (MoSi) is used as an optical shield layer and spin-on glass (SOG) as a phase-shifter layer. Chromium is employed as an etch-stopper during SOG etching. Cr etch-stopper will be removed at the end of tiie process, therefore all optical problems related to an etch-stopper are avoided. This Cr etch-stopper is also useful in inspection and repair of shifter remaining defects. At first, we will describe the fabrication process including the shifter-defect inspection and repair. Secondary, we will discuss the phase-shifting mask accuracy and its influence to the printed resist pattern when using the alternating type phase-shifting mask. Lastly,we will mention the application result of development of lithography for 64Mbit DRAM using this process.

Organotin-containing resists (TMAR) for X-ray lithography

The newly synthesized polymers containing organotin indicate higher sensitivities (2500 mJ/cm2) to synchrotron radiation X-ray (SR X-ray). The sensitivities and the imaging types depend on the amount of tin atoms incorporated in the polymers. Their resistance of the O2 gas reactive ion etching is 50 times higher in comparison with poly(methyl methacrylate) (PMMA). The results for electron beam (EB) are also reported.

Electron Beam Direct Writing Technologies for 0.3-μm ULSI Devices

Electron beam direct writing technologies for 0.3-µm devices are studied in this paper. In order to prevent charging effects, TQV, which is a varnish consisting of 7, 7, 8, 8-tetracyano quino dimethane complex salt, has been coated on the top layer of a trilayer resist system. The effectiveness of TQV coating is indicated by the experimental results obtained from test patterns. A proximity effect correction system with several strategies to reduce the correction time and output data volume has been developed. These technologies have been adopted for the fabrication of ULSI circuit patterns with the dimension of about 0.3 µm. The calculation time and the output data volume of a proximity effect correction are reduced considerably by using new methods. It is revealed that 0.3-µm ULSI patterns can be precisely fabricated by these new technologies.