Satoshi Tazawa

A general characterization and simulation method for deposition and etching technology

A topography simulation system and a six-parameter unified process model are proposed for general characterization of deposition and etching technology. This system is fit to use experimentally. This model precisely expresses the process characteristics of deposition and etching equipment. A surface movement vector calculation method suitable for the unified process model is also given. This method is used for calculating cross-sectional profiles including convex and concave corners, and for general LSI processes where deposition and etching reactions occur simultaneously. The parameters can be extracted from experimental results. The extraction method is also introduced. The simulated results agree well with the experimental ones of sputter deposition and bias-ECR (electron cyclotron resonance) deposition. >

A high-speed 2-D topography simulator based on a pixel model

A high-speed two-dimensional (2-D) topography simulator which operates in X-Windows has been developed. This program, named TIGER (Topography Image GEneration Routine), uses a newly developed pixel model, in which regions of the same material are depicted by pixels with the same value (i.e. the same color) and material boundaries are regarded as color boundaries. New cross-sectional profiles are sequentially created by drawing basic geometrical figures on a cross-sectional profile of a former process step. No complex operations are required for boundary line definition, such as loop removal. Realistic cross sections of an LSI with three interconnection layers and an SST transistor with a complex structure were created by this simulator. The total simulation time is only one or two minutes for all the processing steps of an LSI.

Suppression of Parasitic Bipolar Action and Improvement of Hot-Carrier Reliability in Fully-Depleted Metal-Oxide-Semiconductor Field Effect Transistors on SIMOX (Separation by IMplanted Oxygen) Introducing Recombination Centers near Source Junction

Fully-depleted metal-oxide-semiconductor field effect transistors (MOSFETs) fabricated on a SIMOX (Separation by IMplanted Oxygen) wafer are very promising devices for next-generation low-power high-speed LSIs. However, it is essential to suppress parasitic bipolar action in order to improve source-drain breakdown voltage for practical use in LSIs except for extremely low-voltage-operated applications of less than around 1 V. In this paper, a new suppression method of parasitic bipolar action is proposed, which uses recombination centers near the source junction. Using a two-dimensional (2-D) device simulator, the effects of recombination centers are analyzed, and an effective and stable position for the region containing recombination centers is clarified. Moreover, the effectiveness of the new method is experimentally verified using Ar ion-implantation into the source/drain regions, to introduce the recombination centers. The new method is also remarkably effective in improving hot-carrier reliability, because a hot-carrier degradation mode peculiar to MOSFETs/SOI is able to be suppressed by it.

Application of two-dimensional process/device simulation for evaluating MOSFET fabrication processes

Abstract Applications of a two-dimensional process/device simulator are presented for evaluating the fabrication conditions of MOSFETs. By comparing the simulated results with the measured values, variations in the fabrication sequence have been found. In the analytical mode, a checkup flow is proposed for determining anomalous device structure parameters, such as channel length and gate-oxide thickness. For optimization, the main cause of fluctuating device performance is found automatically. The simulation results confirm that both analysis and optimization modes are effective for identifying variations in the fabrication conditions.

A Compound Semiconductor Process Simulator and its Application to Mask Dependent Undercut Etching

This paper describes a process simulator that is designed to describe the etching and deposition processes used in constructing compound semiconductors, which have at least two different atomic species. This nature dictates a very different response to compound semiconductor process from the silicon process. One of the most remarkable processes in compound semiconductors is the reverse-mesa formation. This simulator successfully represents the mesa and the reverse mesa profiles that are often observed after chemical etching. The mask material dependence of the undercut etching can also be simulated with a good agreement between the experimental and the simulated shapes.

Application Of A Graph Description Method For Structural And Electrical Analysis Of VLSIs

A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.