Savas Kaya

Intrinsic parameter fluctuations in decananometer MOSFETs introduced by gate line edge roughness

In this paper, we use statistical three-dimensional (3-D) simulations to study the impact of the gate line edge roughness (LER) on the intrinsic parameters fluctuations in deep decananometer (sub 50 nm) gate MOSFETs. The line edge roughness is introduced using a Fourier synthesis technique based on the power spectrum of a Gaussian autocorrelation function. In carefully designed simulation experiments, we investigate the impact of the rms amplitude /spl Delta/ and the correlation length /spl Lambda/ on the intrinsic parameter fluctuations in well scaled, but simple devices with fixed geometry as well as the channel length and width dependence of the fluctuations at fixed LER parameters. For the first time, we superimpose in the simulations LER and random discrete dopants and investigate their relative contribution to the intrinsic parameter fluctuations in the investigated devices. For particular MOSFET geometries, we were able to identify the regions where each of these two sources of intrinsic parameter fluctuations dominates.

Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs

Intrinsic parameter fluctuations introduced by discreteness of charge and matter will play an increasingly important role when semiconductor devices are scaled to decananometer and nanometer dimensions in next-generation integrated circuits and systems. In this paper, we review the analytical and the numerical simulation techniques used to study and predict such intrinsic parameters fluctuations. We consider random discrete dopants, trapped charges, atomic-scale interface roughness, and line edge roughness as sources of intrinsic parameter fluctuations. The presented theoretical approach based on Greens functions is restricted to the case of random discrete charges. The numerical simulation approaches based on the drift diffusion approximation with density gradient quantum corrections covers all of the listed sources of fluctuations. The results show that the intrinsic fluctuations in conventional MOSFETs, and later in double gate architectures, will reach levels that will affect the yield and the functionality of the next generation analog and digital circuits unless appropriate changes to the design are made. The future challenges that have to be addressed in order to improve the accuracy and the predictive power of the intrinsic fluctuation simulations are also discussed.

Intrinsic threshold voltage fluctuations in decanano MOSFETs due to local oxide thickness variations

Intrinsic threshold voltage fluctuations introduced by local oxide thickness variations (OTVs) in deep submicrometer (decanano) MOSFETs are studied using three-dimensional (3-D) numerical simulations on a statistical scale. Quantum mechanical effects are included in the simulations employing the density gradient (DG) formalism. The random Si/SiO/sub 2/ and gate/SiO/sub 2/ interfaces are generated from a power spectrum corresponding to the autocorrelation function of the interface roughness. The impact on the intrinsic threshold voltage fluctuations of both the parameters used to reconstruct the random interface and the MOSFET design parameters are studied using carefully designed simulation experiments. The simulations show that intrinsic threshold voltage fluctuations induced by local OTV become significant when the dimensions of the devices become comparable to the correlation length of the interface. In MOSFETs with characteristic dimensions below 30 nm and conventional architecture, they are comparable to the threshold voltage fluctuations introduced by random discrete dopants.

iWISE: Inter-router Wireless Scalable Express Channels for Network-on-Chips (NoCs) Architecture

Network-on-Chips (NoCs) paradigm is fast becoming a defacto standard for designing communication infrastructure for multicores with the dual goals of reducing power consumption while improving performance. However, research has shown that power consumption and wiring complexity will be two of the major constraints that will hinder the growth of future NoCs architecture. This has resulted in the investigation of emerging technologies and devices to alleviate the power and performance bottleneck in NoCs. In this paper, we propose iWISE, an inter-router wireless scalable express channels for NoCs architecture that minimizes the power consumption via hybrid wireless communication channels, reduces the area overhead with smaller routers and shared buffers, and improves performance by minimizing the hop count. We compared our network to leading electrical and wireless topologies such as mesh, concentrated mesh, flattened butterfly and other wireless hybrid topologies. Our simulation results on real applications such as Splash-2, PARSEC, and SPEC2006 for 64 core architectures indicate that we save 2X power and 2X area while improving performance significantly. We show that iWISE can be further scaled to 256 cores while achieving a 2.5X performance increase and saving of 2X power when compared to other wireless networks on synthetic workloads.

Effective mobilities in pseudomorphic Si/SiGe/Si p-channel metal-oxide-semiconductor field-effect transistors with thin silicon capping layers

The room-temperature effective mobilities of pseudomorphic Si/Si0.64Ge0.36/Si p-metal-oxidesemiconductor field effect transistors are reported. The peak mobility in the buried SiGe channel increases with silicon cap thickness. It is argued that SiO2/Si interface roughness is a major source of scattering in these devices, which is attenuated for thicker silicon caps. It is also suggested that segregated Ge in the silicon cap interferes with the oxidation process, leading to increased SiO2/Si interface roughness in the case of thin silicon caps.

Optimization of RF linearity in DG-MOSFETs

RF linearity of double-gate (DG) MOSFETs is investigated using accurate two-dimensional simulations. It is shown that the asymmetric DG-MOSFET is more linear than the symmetric counterpart and that DG-MOSFET linearity can be improved by a careful optimization of channel thickness, nonuniform doping profile and gate work function. For optimum linearity, a nonuniform doping profile and a thick (/spl sim/20 nm) silicon-on-insulator (SOI) layer is required. An intuitive description of this optimization is presented.

Analysis of Statistical Fluctuations due to Line Edge Roughness in sub-0.1μm MOSFETs

We present a full-3D statistical analysis of line edge roughness (LER) in sub-0.1 μm MOSFETs. The modelling approach for line edges and the parameters used in the analysis take into account the statistical nature of the roughness. The results indicate that intrinsic fluctuations in MOSFETs due to LER become comparable in size to random dopant effects and can seriously inhibit scaling below 50 nm.

Wireless networks-on-chips: architecture, wireless channel, and devices

Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some of the key challenges with WINoC implementation, and also describe our example design, iWISE, which is a scalable wireless interconnect design. We show that the integration of wireless interconnects with wired interconnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.

Low-Power Tunable Analog Circuit Blocks Based on Nanoscale Double-Gate MOSFETs

We illustrate unique examples of low-power tunable analog circuits built using independently driven nanoscale DG-MOSFETs, where the top gate response is altered by application of a control voltage on the bottom gate. In particular, we provide examples for a single-ended CMOS amplifier pair, a Schmitt trigger circuit and a operational transconductance amplifier C filter, circuit blocks essential for low-noise high-performance integrated circuits for analog and mixed-signal applications. The topologies and biasing schemes explored here show how the nanoscale DG-MOSFETs may be used for efficient, tolerant and smaller circuits with tunable characteristics.

MOS gated Si:SiGe quantum wells formed by anodic oxidation

We have used electrochemical anodic oxidation to form gate oxides on strained n-channel Si:SiGe quantum wells. The oxides are characterized by current-voltage and capacitance-voltage measurements. Comparison of measured and calculated electron sheet densities in the quantum well, indicates that the oxide growth does not cause degradation of the Si:SiGe material. This is confirmed by low-temperature measurements of the electron mobility and sheet density in the quantum well.