Soumyasanta Laha

Wireless networks-on-chips: architecture, wireless channel, and devices

Wireless networks-on-chips (WINoCs) hold substantial promise for enhancing multicore integrated circuit performance, by augmenting conventional wired interconnects. As the number of cores per IC grows, intercore communication requirements will also grow, and WINoCs can be used to both save power and reduce latency. In this article, we briefly describe some of the key challenges with WINoC implementation, and also describe our example design, iWISE, which is a scalable wireless interconnect design. We show that the integration of wireless interconnects with wired interconnects in NoCs can reduce overall network power by 34 percent while achieving a speedup of 2.54 on real applications.

A New Frontier in Ultralow Power Wireless Links: Network-on-Chip and Chip-to-Chip Interconnects

This paper explores the general framework and prospects for on-chip and off-chip wireless interconnects implemented for high-performance computing (HPC) systems in the context of micro power wireless design. HPC interconnects demand very high (≥ 10 Gb/s) transmission rates using ultraefficient (~ 1 pJ/bit) transceivers over extremely short (≤ 100 cm) ranges. In an attempt to design such wireless interconnects, first a model for the wireless communication channel properties is developed. The use of CMOS-based energyefficient on-off keying (OOK) transceiver architectures operating in the 60-90 GHz bands is considered as a practical solution. In order to address strict performance requirements of wireless HPC interconnects, and taking advantage of the recent developments in device scaling, compact low-power and innovative circuits based on novel double-gate MOSFETs (DG-MOSFETs) are proposed in the implementation of the architecture. The performance of a compact low-noise amplifier (LNA) design using common source (CS) inductive degeneration with 32 nm DGMOSFETs is investigated by quantitative analysis and simulation. The proposed inductor-less two-stage cascode cascade LNA is optimized for 90 GHz operation and has the advantage of gain switching over its CMOS counterpart without the use of additional switching transistors, which makes it remarkably power efficient and faster. As further examples of efficient and compact DG-MOSFET circuits for OOK transceiver design, a three-stage CS 5 dB tunable power amplifier operating up to 90 GHz, and a novel 90 GHz voltage controlled oscillator are also presented. This is followed by the proposal of an array of four monopole antennas studied using full-wave EM solver.

Energy-efficient adaptive wireless NoCs architecture

With the increasing number of cores in chip multiprocessors, the design of an efficient communication fabric is essential to satisfy the bandwidth and energy requirements of multi-core systems. Scalable Network-on-Chip (NoC) designs are quickly becoming the standard communication framework to replace bus-based networks. However, the conventional metallic interconnects for inter-core communication consume excess energy and lower throughput which are major bottlenecks in NoC architectures. On-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose an adaptable wireless Network-on-Chip architecture (A-WiNoC) that uses adaptable and energy efficient wireless transceivers to improve network power and throughput by adapting channels according to traffic patterns. Our adaptable algorithm uses link utilization statistics to re-allocate wireless channels and a token sharing scheme to fully utilize the wireless bandwidth efficiently. We compare our proposed A-WiNoC to both wireless/electrical topologies with results showing a throughput improvement of 65%, a speedup between 1.4-2.6X on real benchmarks, and an energy savings of 25-35%.

A-WiNoC: Adaptive Wireless Network-on-Chip Architecture for Chip Multiprocessors

With the rise of chip multiprocessors, an energy-efficient communication fabric is required to satisfy the data rate requirements of future multi-core systems. The Network-on-Chip (NoC) paradigm is fast becoming the standard communication infrastructure to provide scalable inter-core communication. However, research has shown that metallic interconnects cause high latency and consume excess energy in NoC architectures. Emerging technologies such as on-chip wireless interconnects can alleviate the power and bandwidth problems of traditional metallic NoCs. In this paper, we propose A-WiNoC, a scalable, adaptable wireless Network-on-Chip architecture that uses energy efficient wireless transceivers and improves network throughput by dynamically re-assigning channels in response to bandwidth demands from different cores. To implement such adaptability in our network at run-time, we propose an adaptable algorithm that works in the background along with a token sharing scheme to fully utilize the wireless bandwidth efficiently. Since no wireless NoC design has been completely realized with current technology, we describe technology trends in designing energy-efficient wireless transceivers with emerging technologies. We compare our proposed A-WiNoC to both wireless and wired topologies at 64 cores, with results showing a 1.4-2.6× speedup on real applications and a 54 percent improvement in throughput for synthetic traffic. Using Synopsys Design Compiler, our results indicate that A-WiNoC saves 25-35 percent energy over other state-of-the-art networks. We show that A-WiNoC can scale to 256 cores with an energy improvement of 21 percent and a saturation throughput increase of approximately 37 percent.

Energy efficient modulation for a wireless network-on-chip architecture

As both power consumption and leakage currents will limit the scalability of future massively integrated computational systems, research into emerging technologies and devices to replace traditional metallic interconnects has become critical. In this paper we propose an initial implementation for a hybrid wireless network-on-chip (WiNoC) interconnect architecture, named iWISE, for current chip multiprocessors (CMPs). iWISE combines wired interconnects with wireless links that use both frequency and time division multiplexing to offer a balanced, flexible, orthogonal wireless data transfer among cores. We provide a basic description of the iWISE architecture and describe a practical solution for the implementation of wireless interconnects based on an on-off keying (OOK) modulator using ultra-compact Double Gate (DG) CMOS devices. The proposed OOK modulator takes advantage of DG-CMOS devices especially in building compact modulation and tunable amplification circuitry. Real applications from the benchmark suite PARSEC as well as synthetic traffic show an improvement in performance as well as a savings in power.

60 GHz OOK Transmitter in 32 nm DG FinFET technology

There are several 60 GHz transceiver architectures that have been explored and reported in the past employing the On Off Keying (OOK) Modulation. All of these designs are primarily based on the conventional bulk CMOS architecture. In this paper, we propose a power efficient double gate (DG) MOSFET based OOK Transmitter in 32 nm DG FinFET technology. The proposed novel OOK modulator consists of only two DG-MOSFETs, making the circuit extremely power and area efficient. The LC oscillator can be tuned via back gate bias to vary the amplitude as well as frequency. The phase noise of the oscillator has a value of -133 dBc/Hz which is comparable to LC oscillator in conventional CMOS. The wide band power amplifier (PA) in addition to tunable characteristics also excels in other figures of merit such as gain (6-8 dB) and 3-dB bandwidth (>; 40 GHz) when compared to some recent works.

Kilo-core Wireless Network-on-Chips (NoCs) Architectures

As energy-efficiency and high-performance of Networks-on-Chips (NoCs) communication fabric have become critical, limited bandwidth and fundamental signaling limitations of metallic interconnects have forced academia and industry to consider emerging technologies such as wireless interconnects as an alternate solution. Wireless interconnects offer multiple degrees of freedom for communication without any area overhead for waveguides/wires, and can be built on already available CMOS-RF platforms. In this paper, we propose High-Core WiNoC (HCWiNoC) that can scale to 1000+ cores while mitigating the three critical challenges of WiNoC - limited bandwidth, multi-channel interference and transceiver efficiency - to build an end-to-end solution. First, we describe our row-column HCWiNoC architecture where wireless channels are shared via tokens and wired channels are employed for shorter distances. Second, using HFSS design tool from Ansys, we design monopole and dipole antennas and quantify the multi-channel path loss and dispersion in our WiNoC structure. Third, we describe our transceivers, which consist of local oscillators, on-off keying (OOK) modulators/demodulators, power amplifiers (PA), low-noise amplifiers (LNA) and filters in 65 nm RF-CMOS design from IBM in Cadence Virtuoso. Further, based on our design and published results, we project energy efficiency trends for 32 and 22 nm technology nodes. Our cycle-accurate simulation results on synthetic traffic for 1024 cores indicate that we can double the throughput while consuming 20% lesser power than state-of-the-art WiNoC architecture.

On ultra-short wireless interconnects for NoCs and SoCs: Bridging the ‘THz Gap’

We review and analyze the critical features of ultra-short range wireless links. These features will be required for advancing NoC and SoC integration to the next level, as transistor scaling and hetero-integration on silicon substrates are expected to reach their full potential by the end of the decade. Based on published transceiver data, the scalable wireless NoCs for multi-core processors and reconfigurable networks for SoCs are within reach of Si/SiGe BiCMOS technology in the next few technology generations. However, before such THz-band CMOS wireless transceivers can become reality and work efficiently, compact high-gain on-chip antennas, high-density on-chip inductors with magnetic cores, and tunable-gain LNAs/PAs that can lower power consumption will be necessary.

Double gate MOSFET based efficient wide band tunable power amplifiers

Performance, tunability and efficiency of double gate MOSFET (DG-MOSFET) based power amplifiers (PA) are investigated. Specifically, we propose two different wide-band PA topologies with 45 nm long DG-MOSFET and study their performance via computer simulations. The first one involves a modified Darlington cascode configuration with a peak gain of ~26 dB for a 3-dB bandwidth ≥ 30 GHz. The gain flatness is less than 20% in this range. The second topology reported is a three-stage common-source wide band PA that gives a peak gain of 8 dB in 60-90 GHz band. In both designs, one can utilize the back-gate bias for gain control of 10 dB and 6 dB, respectively, a unique capability not found in comparable amplifiers built with single gate MOSFET architectures. We also provide a comparison of the simulated performance figures of merit for the DG-MOSFET amplifiers with those reported for the conventional CMOS based PAs reported recently, which shows that proposed designs are either comparable or better than the standard CMOS counterparts in all figures of merits considered.

Optimum biasing and design of high performance double gate MOSFET RF mixers

The optimum biasing conditions and structural design parameters for novel nano-scale radio frequency mixers based on single double gate MOSFET is investigated. Our objective is to analyze and identify the correlation of the conversion gain of the mixer circuit with the signal conditions at the local oscillator as well as different device parameters, such as the gate length (Lgate), doping concentration (NA) and body thickness (tSi), thus minimizing signal loss and power consumption. The most important figure of merit in the mixer performance is found to be the LO DC bias that determines the level of non-linearity in the transconductance response. Furthermore, we observe that in properly designed double gate MOSFETs (Lgate ≥ 3tSi), Lgate and NA have limited impact on the conversion gain of the mixer, while tSi has a more significant role to play. Although the mixing performance of double gate MOSFETs is ultimately limited by the short channel effects perpetrated by any given structural constraint, an optimum body thickness tSi exists in each case to maximize the conversion gain. Thus, we illustrate how 2D and quantum-corrected simulations can identify the optimum body thickness and optimum bias conditions in such compact nano-scale mixers.