Se-Jang Oh

Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques

This paper characterizes the electrical performance of a probe card that is currently used for the test of memory devices operating at 300 MHz. The large printed circuit board assembly of the probe card has been found to consume 70% of the total signal transmission loss. We propose a simultaneous application of the back-drilling and the equalization techniques that greatly improve the signal integrity (SI) by reduction of the insertion loss and by planarization of the frequency response, respectively. These techniques are very simple and easy to be implemented by the numerical control of the drilling equipment and the surface mount technology. The Δ 3-dB bandwidth has greatly been improved from 0.66 GHz of the conventional probe card to 2.46 GHz after both of the equalization and the back-drilling. We also achieved 53% reductions of the transition times (Tr/Tf) and 51% improvement of the peak-to-peak jitter. We expect the simultaneous application of the back-drilling and the equalization be effectively used for further improvements of current wafer-level probe card performance.

A Serial Optical Link Based Memory Test System for High-Speed and Multi-Parallel Test

A novel memory optical test solution is proposed and experimentally evaluated for at-speed DDR2-SDRAM test using a commercial automatic test equipment (ATE). Combination of an optical signal splitting scheme and SerDes (Serializer/De-Serializer) technique based on FPGA (Field programmable gate array) allows the high-speed multi-parallel memory test with reduced channel resources. Owing to the SerDes, optical fiber channels are reduced by more than 87 percent and the number of optical modules including transmitter/receiver dramatically decrease to 95 percent, compared with a conventional optical test interface system. Furthermore, the proposed system can optically expand the tester resource by 4 times using a 1 × 4 optical splitting scheme. We evaluated the signal integrity of 28 layer PCB operating at 3.125 Gbps with three-dimension electromagnetic simulation to obtain more reliable system for memory testing. Consequently, for the first time to the best of our knowledge, we realized an optical SerDes interconnect system for a memory test tester and demonstrated an actual write/read function test of DDR2-SDRAM.

Low-Complexity Off-Chip Skew Measurement and Compensation Module (SMCM) Design for Built-Off Test Chip

Skew calibration and compensation are critical ATE features for reliable functional test, particularly for applications such as memory chips. This paper presents a new Time-to-Digital Converter (TDC) design for off-chip skew calibration from Time Domain Reflectometry (TDR)measurements. It consists of coarse and fine parts which enable the circuit to detect a large skew range with high resolution. Circuit complexity is reduced through use of the proposed automatic edge detection methods which control coarse/fine operations. We also present skew compensation circuits which can de-skew off-chip signals based on the skew calibration. The TDC occupies a small area, making it suitable for implementation in a Built-Off Test (BOT) chip.The circuits were implemented using a 130nm technology in a Built-Off Test Interface (BOTI) developed for 800Mbps DDR2 memory functional test.