Ki-Sang Kang

Signal Integrity Improvements of a MEMS Probe Card Using Back-Drilling and Equalizing Techniques

This paper characterizes the electrical performance of a probe card that is currently used for the test of memory devices operating at 300 MHz. The large printed circuit board assembly of the probe card has been found to consume 70% of the total signal transmission loss. We propose a simultaneous application of the back-drilling and the equalization techniques that greatly improve the signal integrity (SI) by reduction of the insertion loss and by planarization of the frequency response, respectively. These techniques are very simple and easy to be implemented by the numerical control of the drilling equipment and the surface mount technology. The Δ 3-dB bandwidth has greatly been improved from 0.66 GHz of the conventional probe card to 2.46 GHz after both of the equalization and the back-drilling. We also achieved 53% reductions of the transition times (Tr/Tf) and 51% improvement of the peak-to-peak jitter. We expect the simultaneous application of the back-drilling and the equalization be effectively used for further improvements of current wafer-level probe card performance.

Wafer-Level Characterization of Probecards using NAC Probing

This paper presents Needle Auto Calibration (NAC) probing technique to measure the electrical characteristics of Probecard for wafer-level test. Probecard needle alignment and probing tasks, which are generally known to be hard and time-consuming, can be done easily through automatic Probecard aligning function of NAC. The inaccuracy problem during measurements by NAC probing due to difficulties of calibration is compensated by adapter characterization and de-embedding techniques. According to our experimental results, the inaccuracies of group delay, insertion loss and phase characteristic are decreased from 30.4% to 2.71%, from 1.75% to 0.53%, and from 35.2% to 1.32%, respectively.

A New Wafer Level Latent Defect Screening Methodology for Highly Reliable DRAM Using a Response Surface Method

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposed methodology consists of a defect-based wafer burn-in (DB-WBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.