Sean S. Eilert
Intel
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Publication
Featured researches published by Sean S. Eilert.
international solid-state circuits conference | 2005
Mase J. Taub; Rupinder Bains; Gerald Barkley; Hernan A. Castro; Gregory V. Christensen; Sean S. Eilert; Rich Fackenthal; Hari Giduturi; Matthew Goldman; Chris Haid; Rezaul Haque; Krishna Parat; Steve Peterson; A. Proescholdt; Karthi Ramamurthi; Paul D. Ruby; Balaji Sivakumar; Alec W. Smidt; Balaji Srinivasan; Martin Szwarc; Kerry D. Tedrow; Doug Young
A 2b/cell flash memory in 90 nm triple-well CMOS technology achieves 1.5 MB/s programming and 166 MHz synchronous operation. The design features 2-row programming, optimized program control hardware, 3 transistor x-decoder with negative deselected rows and configurable output buffers. The die is 42.5 mm/sup 2/ with a cell size of 0.076 /spl mu/m/sup 2/.
Archive | 2003
Sean S. Eilert
Archive | 2005
John C. Rudelic; Sean S. Eilert
Archive | 2005
Paul D. Ruby; Sean S. Eilert
Archive | 2004
Sean S. Eilert; John C. Rudelic
Archive | 2006
Sean S. Eilert; Peter Port Coquitlam Leung; Rich Fackenthal
Archive | 2007
Sean S. Eilert; Rodney R. Rozman
Archive | 2004
Sunil R. Atri; Sean S. Eilert
Archive | 2003
Sean S. Eilert; Alec W. Smidt
Archive | 2006
Shekoufeh Qawami; Rodney R. Rozman; Sean S. Eilert
