Sebastian Ehrenreich

Implementation of the CELL Broadband Engine in a 65nm SOI Technology Featuring Dual-Supply SRAM Arrays Supporting 6GHz at 1.3V

The 65nm CELL Broadband Enginetrade design features a dual power supply, which enhances SRAM stability and performance using an elevated array-specific power supply, while reducing the logic power consumption. Hardware measurements demonstrate low-voltage operation and reduced scatter of the minimum operating voltage. The chip operates at 6GHz at 1.3V and is fabricated in a 65nm CMOS SOI technology.

A 4R2W register file for a 2.3GHz wire-speed POWER™ processor with double-pumped write operation

In multi-ported register files, memory cell size grows quadratically with the total number of ports due to wordline and bitline wiring. Reducing the number of physical access ports in a memory cell can thus lead to significant area and power savings as well as latency improvement. Double-pumped register files operate access ports twice in a single clock period to reduce area by halving the number of physical ports in the memory cell — a technique often confined to low-frequency applications. Replication of a memory cell in separate arrays halves the number of physical read ports in each copy. In this work, double-pumped write ports and replicated read ports are applied to a 4R2W register file in a highperformance microprocessor product [1]. This paper describes detailed implementation and measured hardware characteristics of this array and demonstrates a fast error correction scheme. The techniques used balance high efficiency and low latency and thus differ from previous work, in which double-pumped ports perform a write followed by a read in a very large register file [2] or where write ports are double-pumped without cell-level read port reduction [3].

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

The 65 nm cell broadband enginetrade (cell BE) is a multi-core SoC, implemented in a high performance SOI technology featuring a separate dual power supply for SRAM arrays to improve stability and performance using an elevated voltage. A new method is shown to analyze the SRAM cell under application conditions which was used to tune the cell for stability, write-ability and performance. An improved write scheme is shown which widens the overall functional window and allows setting the power/performance point of the arrays independently of the surrounding logic. Hardware measurements demonstrate the advantages of the dual power supply under different aspects.

The vector fixed point unit of the synergistic processor element of the cell architecture processor

A vector fixed point unit (FXU) is designed to speed up multi-media processing. The FXU implements SIMD style integer arithmetic and permute operations. The adder, rotator and permute structure enables the use of static circuits only. The FXU was fabricated using IBM 90nm CMOS SOI technology

The Design and Implementation of a Low-Overhead Supply-Gated SRAM

The paper reports a virtual supply domain control technique for low-leakage SRAMs. This method encompasses cell-based sleep circuit tiling, sequentially regulated power-on/off, and flexible domain interfacing. The usual overhead associated with driving sleep transistors is significantly reduced by powering on/off gradually. Over 260times and 3times leakage reduction is observed in 65nm-technology hardware for hard and soft gating, respectively, including the leakage of control and drive circuits. Measured virtual domain power-on latency is compatible with high-frequency designs