Sebastian Glab

Characterization of high resolution CMOS monolithic active pixel detector in SOI technology

Novel CMOS monolithic pixel detectors designed at KEK and fabricated at Lapis Semiconductor in 0.2 μm Silicon-on-Insulator (SOI) technology are presented. A thin layer of silicon oxide separates high and low resistivity silicon layers, allowing for optimization of design of detector and readout parts. Shallow wells buried under the oxide in the detector part screen the entire pixel electronics from electrical field applied to the detector. Several integration type SOI pixel detectors have been developed with pixel sizes 8–20 μm. The general features of 14 × 14 μm2 detectors designed on different wafers (CZ-n, FZ-n and FZ-p) were measured and compared. The detector performance was studied under irradiation with visible and infra-red laser, and also X-ray ionizing source. Using X-rays from an Am-241 source the noise of readout electronics was measured at different working conditions, showing the ENC in the range of 88–120 e−. The pixel current was calculated from average DC pedestal shift while varying the pixel integration time. The operation of the detector was studied under partial and full depletion conditions. The effects of temperature and detector bias voltage on noise and leakage current were studied. Characteristics of an ADC integrated in the front-end chip are also presented.

Development of pixel detector in Novel sub-micron technology SOI CMOS 200 nm

This paper presents the design of a new monolithic Silicon-On-Insulator pixel sensor in 200 nm SOI CMOS technology. The main application of the proposed pixel detector is the spectroscopy, but it can also be used for the minimum ionising particle (MIP) tracking in particle physics experiments. For this reason the overriding goal of the project was to increase the signal to noise ratio of the readout circuit and sensor.

Fully differential charge to time converter and fast shaper readout circuit with gain compensation for SiPM

The implementation of fully differential readout method for Silicon Photomultipliers (SiPM) is presented. The front-end circuit consists of preamplifier with fast shaper and Charge to Time Converter (QTC). The fast shaper generates unipolar pulse. The peaking time for single photoelectron is equal to 3.6ns and the FWHM is 3.8ns. The pulse width of the QTC depends on the number of photons. The gain of SiPM is compensated by moderating the bias voltage. The polarization voltage is adjusted indirectly by tuning the output common mode voltage (VOCM) of fully differential amplifier. The advantage of the algorithm is the possibility to set the bias of each SiPM in the array independently so they all could operate in similar conditions (have similar gain and dark count rate).

Microflow measurements of antibodies fluorescence using Silicon Photomultipliers

The paper presents research made using acquisition system designed and built by the authors. It consists of Silicon Photomultipliers used for fluorescence light detection, integrated circuit dedicated for Silicon Photomultipliers and FPGA board for data acquisition. Moreover, electronic part of the system is integrated with optical section i.e. semiconductor laser, optical filters, microflow structure and optical fibers. Measured substances are passed through Polydimethylsiloxane (PDMS) microflow structure with microchannel of tens of um diameter and that is where optical detection phase takes place. The substance is stimulated by laser light and its fluorescence is being detected by SiPM. Measurements with fluorescence dyes such as sodium fluoresceinate and BD Biosciences CF series indicate sensitivity of the measurement system on the level of single picogram of the dye in ml of the buffer. CF dyes are being mixed with antibodies such as ANTI-NPR in order to measure sensitivity of the system for various concentrations of the antibody. ANTI-NPR is an antibody that reacts with human natriuretic peptide, a substance that can be found in human blood short after excessive heart effort or heart failure. Measurement system is not designed only for NPR antibody but also e.g. myoglobin, troponin and others. That is why not only single antibody has been measured.

Front-end electronics with fast signal shaper for silicon photomultipliers

The paper describes a CMOS Integrated Circuit designed for interfacing a Silicon Photomultiplier (SiPM) in UMC 180 nm technology. It features a full signal processing architecture containing Pole-Zero Cancellation (PZC) circuit, Peak Detector and Hold circuit and Comparators which one of main purposes is the coincidence recognition. Front-end electronics consists of two separate channels one for each SiPM. This along with comparators enables to introduce the coincidence mode to the system. It can be used e.g. for significant reduction of dark current of SiPM in measurement data. The main characteristic of the chip is its fast signal shaping. After the amplification and PZC correction, pulses corresponding to single particles of light detected by SiPM are 20 ns. Moreover, switching time of the comparators used in the circuit is 2 ns. Preliminary results of the chip measurements are presented and the functionality of the chip is also explained.

Bandgap voltage reference and temperature sensor in novel SOI technology

A bandgap voltage reference together with absolute temperature sensor (PTAT) designed in 200 nm SOI technology is presented in this paper. Three slightly different versions were designed to verify the diode models available in the SOI process. For more extensive SOI process study the chip was fabricated on three different substrates. The bandgap reference circuit generates Vref = 1.27 V with 10 mV chip to chip spread. The best bandgap version has temperature coefficient -35 μV/K. Circuit design, simulations and comparison with measured performance are presented.

Design and simulations of the 10-bit SAR ADC in novel sub-micron technology 200 nm SOI CMOS

This paper presents the design of the 10-bit Successive Approximation Register Analog-to-Digital Converter (SAR ADC) achieving 20 MHz sampling frequency at a power consumption of about 900 μW and 1.8 V power supply. The ADC was designed in 200 nm Silicon-On-Insulator (SOI) CMOS process. The SOI is one of the most advanced CMOS technology that allows to reduce the parasitic capacitances, limit power dissipation and increase speed of the system.

Low intensity fluorescence light measurements using Silicon Photomultiplier with dedicated front-end ASIC

The paper presents front-end ASIC and measurements of low intensity fluorescence light using Silicon Photomultiplier. Front-end ASIC is dedicated device for amplifying and shaping signals from Silicon Photomultipliers. Measurement method is described. Fluorescence intensity for sodium fluoresceinate and resorufin in different concentrations is presented. Sensitivity limit is studied.

Self-Calibrating Gain Stabilization method for applications using Silicon Photomultipliers

Performance of Silicon Photomultipliers (SiPM) [1] strongly depends on bias voltage and temperature. The key aspect in low light detection is precision and stability of SiPMs gain. These requirements can be met by delivering accurate bias and keeping temperature on constant level. It is not very demanding task in case of single SiPM. However, in applications consisting of thousands of SiPMs it is much more problematic or even impossible to control the temperature of each detector (e.g. nuclear physics experiments). The paper presents a gain stabilization method that can be applied in multidetector measurements without the need to characterize gain-temperature-bias functions and parameters of all detectors used in the experiment.