Sebastian Höppner

VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology

This brief presents a bang-bang all-digital phase-locked loop (ADPLL) clock generator for multiprocessor system-on-chip applications in Globalfoundries 28-nm superlow-power CMOS technology. The circuit features a single-shot phase synchronization scheme for instantaneous phase lock after power-up. This feature is used for fast frequency search during lock-in, resulting in less than 1-μs initial lock time and the capability of instantaneous restart. The ADPLL provides a wide range of output clocks from 83 MHz to 2 GHz and exhibits 31-ps accumulated jitter with 3-ps period jitter at 2 GHz. It occupies an area of only 0.00234 mm2 and consumes 0.64 mW from a 1.0-V supply.

10.7 A 105GOPS 36mm 2 heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS

Modern mobile communication systems face conflicting design constraints. On the one hand, the expanding variety of transmission modes calls for highly flexible solutions supporting the ever-growing number and diversity of application requirements. On the other hand, stringent power restrictions (e.g., at femto base stations and terminals) must be considered, while satisfying the demanding performance requirements. In order to cope with these issues, existing SDR platforms, e.g. [1-2], propose an MPSoC with a heterogeneous array of processing elements (PEs). MPSoC solutions provide programmability and parallelism yielding flexibility, processing performance and power efficiency. To schedule the resources and to apply power gating, a static approach is employed. In contrast, we present a heterogeneous MPSoC platform (Tomahawk2) with runtime scheduling and fine-grained hierarchical power management. This solution can fully adapt to the dynamically varying workload and semi-deterministic behavior in modern concurrent wireless applications. The proposed dynamic scheduler (CoreManager, CM) can be implemented either in software on a general-purpose processor or on a dedicated application-specific hardware unit. It is evident that the software approach offers the highest degree of flexibility; however, it may become a performance-bottleneck for complex applications. A high-throughput ASIC was presented in [3], but this solution does not permit scheduling algorithms to be adjusted. In this work, these limitations are overcome by implementing the CM on an ASIP.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm2 it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by per-core dynamic voltage and frequency scaling (DVFS) and by employing a globally-asynchronous, locally-synchronous (GALS) system architecture in which distribution of a synchronous high-speed clock is not required. For global on-chip communication this presents major challenges due to the need for reliable data synchronization, high bandwidth requirements and speed limiting RC effects on long wires. It has been shown recently that low-swing differential on-chip links provide highest bandwidth, low energy-per-bit and uninterrupted transfers over lengths up to 10mm [1-3, 6]. Capacitively-driven links are promising because of their built-in pre-emphasis thereby countervailing the low-pass behavior of long on-chip wires [1, 4-5]. However, all of these existing implementations focus mainly on the transmission line itself. The capacitively-driven links are not able to forward a stoppable clock signal as there is no well defined differential DC level on the wires with no data or clock activity. In addition, clocking is not reported [5] or fully synchronous, which means a high-speed clock must be distributed globally on-chip. This work provides a solution for capacitively-driven links with a parallel DC resistive divider to allow forwarded clocking with complete gating capability.

A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits

A switched-capacitor (SC) neuromorphic system for closed-loop neural coupling in 28 nm CMOS is presented, occupying 600 um by 600 um. It offers 128 input channels (i.e., presynaptic terminals), 8192 synapses and 64 output channels (i.e., neurons). Biologically realistic neuron and synapse dynamics are achieved via a faithful translation of the behavioural equations to SC circuits. As leakage currents significantly affect circuit behaviour at this technology node, dedicated compensation techniques are employed to achieve biological-realtime operation, with faithful reproduction of time constants of several 100 ms at room temperature. Power draw of the overall system is 1.9 mW.

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs

This paper presents a power management architecture for MPSoCs that allows fast switching between multiple onchip supply voltage levels per core. Operation is based on distinct scenarios for power-up and supply level change, with individual numbers of pre-charge switches for supply noise reduction. The power management controller is highly configurable for adaption to a wide range of supply network parasitics in heterogeneous MPSoCs. This architecture has been validated by measurements in 65nm CMOS technology. Power-up and DVFS level changes can be performed in less than 20ns with reduced parasitic voltage drop of active cores.

Switched-capacitor realization of presynaptic short-term-plasticity and stop-learning synapses in 28 nm CMOS.

Synaptic dynamics, such as long- and short-term plasticity, play an important role in the complexity and biological realism achievable when running neural networks on a neuromorphic IC. For example, they endow the IC with an ability to adapt and learn from its environment. In order to achieve the millisecond to second time constants required for these synaptic dynamics, analog subthreshold circuits are usually employed. However, due to process variation and leakage problems, it is almost impossible to port these types of circuits to modern sub-100nm technologies. In contrast, we present a neuromorphic system in a 28 nm CMOS process that employs switched capacitor (SC) circuits to implement 128 short term plasticity presynapses as well as 8192 stop-learning synapses. The neuromorphic system consumes an area of 0.36 mm2 and runs at a power consumption of 1.9 mW. The circuit makes use of a technique for minimizing leakage effects allowing for real-time operation with time constants up to several seconds. Since we rely on SC techniques for all calculations, the system is composed of only generic mixed-signal building blocks. These generic building blocks make the system easy to port between technologies and the large digital circuit part inherent in an SC system benefits fully from technology scaling.

A 335Mb/s 3.9mm 2 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates

In current and future wireless standards, such as WiMAX, 3GPP-LTE or LTE-Advanced, receiver terminals have to support numerous operating modes for each protocol [1], as well as sophisticated transmission techniques, especially enhanced MIMO detection and iterative forward error correction (FEC). MIMO detection and FEC belong to the most computationally complex parts of the receiver-side baseband signal processing chain. Implementations thereof must have low power consumption, but also be able to interact in a flexible and efficient way in the detection-decoding engine, while at the same time not compromising on the challenging throughput and flexibility requirements associated with 4G standards. In this paper, we present a chip implementation of a MIMO sphere detector combined with a flexible FEC engine, realizing a detection-decoding engine in silicon capable of satisfying 4G requirements with a data rate of 335Mb/s.

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long distance interconnects in the mm range within MPSoCs. Its source synchronous clocking scheme enables application in GALS systems and allows completely stoppable transceiver clocking for low idle power consumption. A capacitive line driver with combined resistive driver for well defined DC swing is employed and analyzed in detail by simulation studies. It is shown that proper DC swing definition is mandatory for robust operation of long links at high data rates. Prototypes of the transceiver over 6 mm bufferless on-chip interconnect are implemented in both 65 nm and 28 nm CMOS technologies. The 65 nm realization achieves an efficiency of 173 fJ/bit/mm at 90 Gbit/s at 1.25 V and 93 fJ/bit/mm at 45 Gbit/s low speed mode at 0.9 V. The 28 nm realization achieves 81 fJ/bit/mm at 72 Gbit/s at 1.05 V and 64 fJ/bit/mm at 36 Gbit/s low speed mode at 0.95 V. The transceiver can be seamlessly integrated as black box point-to-point connection into heterogeneous MPSoC NoCs to enable ultra-compact toplevel floorplan realization and increased energy efficiency. An example of a 20-core MPSoC in 65 nm CMOS technology with 10 serial NoC transceivers is presented.