Stephan Henker

VLSI Implementation of a 2.8 Gevent/s Packet-Based AER Interface with Routing and Event Sorting Functionality

State-of-the-art large-scale neuromorphic systems require sophisticated spike event communication between units of the neural network. We present a high-speed communication infrastructure for a waferscale neuromorphic system, based on application-specific neuromorphic communication ICs in an field programmable gate arrays (FPGA)-maintained environment. The ICs implement configurable axonal delays, as required for certain types of dynamic processing or for emulating spike-based learning among distant cortical areas. Measurements are presented which show the efficacy of these delays in influencing behavior of neuromorphic benchmarks. The specialized, dedicated address-event-representation communication in most current systems requires separate, low-bandwidth configuration channels. In contrast, the configuration of the waferscale neuromorphic system is also handled by the digital packet-based pulse channel, which transmits configuration data at the full bandwidth otherwise used for pulse transmission. The overall so-called pulse communication subgroup (ICs and FPGA) delivers a factor 25–50 more event transmission rate than other current neuromorphic communication infrastructures.

A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology

This paper presents an all-digital phase-locked loop (ADPLL) clock generator for globally asynchronous locally synchronous (GALS) multiprocessor systems-on-chip (MPSoCs). With its low power consumption of 2.7 mW and ultra small chip area of 0.0078 mm2 it can be instantiated per core for fine-grained power management like DVFS. It is based on an ADPLL providing a multiphase clock signal from which core frequencies from 83 to 666 MHz with 50% duty cycle are generated by phase rotation and frequency division. The clock meets the specification for DDR2/DDR3 memory interfaces. Additionally, it provides a dedicated high-speed clock up to 4 GHz for serial network-on-chip data links. Core frequencies can be changed arbitrarily within one clock cycle for fast dynamic frequency scaling applications. The performance including statistical analysis of mismatch has been verified by a prototype in 65-nm CMOS technology.

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS

While continued scaling of feature sizes allows for an ever increasing number of cores in modern MPSoCs, power reduction and meeting on-chip bandwidth requirements are pressing concerns. Energy efficiency can be increased by per-core dynamic voltage and frequency scaling (DVFS) and by employing a globally-asynchronous, locally-synchronous (GALS) system architecture in which distribution of a synchronous high-speed clock is not required. For global on-chip communication this presents major challenges due to the need for reliable data synchronization, high bandwidth requirements and speed limiting RC effects on long wires. It has been shown recently that low-swing differential on-chip links provide highest bandwidth, low energy-per-bit and uninterrupted transfers over lengths up to 10mm [1-3, 6]. Capacitively-driven links are promising because of their built-in pre-emphasis thereby countervailing the low-pass behavior of long on-chip wires [1, 4-5]. However, all of these existing implementations focus mainly on the transmission line itself. The capacitively-driven links are not able to forward a stoppable clock signal as there is no well defined differential DC level on the wires with no data or clock activity. In addition, clocking is not reported [5] or fully synchronous, which means a high-speed clock must be distributed globally on-chip. This work provides a solution for capacitively-driven links with a parallel DC resistive divider to allow forwarded clocking with complete gating capability.

Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput

One of the main challenges in large scale neuromorphic VLSI systems is the design of the communication infrastructure. Traditionally, the neural communication has been done via parallel asynchronous transmission of Address-Event-Representations (AER) of pulses, while the configuration was achieved via off-the-shelf chip connect protocols. Recently, there has been a move towards greater event transmission speed via a serialization of the AER protocols, as well as an integration of both communication and configuration in the same interface. We present the PCB and FPGA design of such an interface for a newly developed waferscale neuromorphic system. The serial event communication of other current approaches has been refined into a packet based synchronous (rather than asynchronous) protocol, which offers better flexibility and bandwidth utilization. A factor 30–100 greater event transmission rate has been achieved. Compared to other approaches, the full communication bandwidth can also be employed for configuration. The system offers additional functionality, such as event storage and replay. Also, a very high degree of mechanical integration has been achieved.

Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks

With the various simulators for spiking neural networks developed in recent years, a variety of numerical solution methods for the underlying differential equations are available. In this article, we introduce an approach to systematically assess the accuracy of these methods. In contrast to previous investigations, our approach focuses on a completely deterministic comparison and uses an analytically solved model as a reference. This enables the identification of typical sources of numerical inaccuracies in state-of-the-art simulation methods. In particular, with our approach we can separate the error of the numerical integration from the timing error of spike detection and propagation, the latter being prominent in simulations with fixed timestep. To verify the correctness of the testing procedure, we relate the numerical deviations to theoretical predictions for the employed numerical methods. Finally, we give an example of the influence of simulation artefacts on network behaviour and spike-timing-dependent plasticity (STDP), underlining the importance of spike-time accuracy for the simulation of STDP.

An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS

This paper presents a network-on-chip (NoC) SerDes transceiver architecture for long distance interconnects in the mm range within MPSoCs. Its source synchronous clocking scheme enables application in GALS systems and allows completely stoppable transceiver clocking for low idle power consumption. A capacitive line driver with combined resistive driver for well defined DC swing is employed and analyzed in detail by simulation studies. It is shown that proper DC swing definition is mandatory for robust operation of long links at high data rates. Prototypes of the transceiver over 6 mm bufferless on-chip interconnect are implemented in both 65 nm and 28 nm CMOS technologies. The 65 nm realization achieves an efficiency of 173 fJ/bit/mm at 90 Gbit/s at 1.25 V and 93 fJ/bit/mm at 45 Gbit/s low speed mode at 0.9 V. The 28 nm realization achieves 81 fJ/bit/mm at 72 Gbit/s at 1.05 V and 64 fJ/bit/mm at 36 Gbit/s low speed mode at 0.95 V. The transceiver can be seamlessly integrated as black box point-to-point connection into heterogeneous MPSoC NoCs to enable ultra-compact toplevel floorplan realization and increased energy efficiency. An example of a 20-core MPSoC in 65 nm CMOS technology with 10 serial NoC transceivers is presented.

A compact on-chip IR-drop measurement system in 28 nm CMOS technology

A sensor system for measuring the power-ground (PG) noise in very large scale integrated circuits is presented. The proposed system utilizes sensor elements with standard cell dimensions enabling high spatial resolution voltage measurements of power and ground rails. Asynchronous sub-sampling is used to directly convert the analog signals into the digital domain inside the sensors to ensure precise waveform acquisition. Timing signals are derived from a all-digital phase-locked-loop (ADPLL) which guarantees accurate low-noise sampling of the supply waveforms. The sensor system has been implemented in a 28nm CMOS test chip. Simultaneous acquisition of voltage drop and ground bounce at 300 probe points within a 120μm × 120μm macro at 62.5 ps time and up to 250μV voltage resolution shows the capabilities of both, high spatial and high temporal resolution measurement of PG noise.

A programmable clock generator HDL softcore

This paper presents a hardware implementation of a fully synthesizable, technology independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter. Frequency control is done by using a robust regulation algorithm to allow a defined lock-in time of at most 8 reference cycles. ASICs in CMOS AMS 0,35 um and UMC 0,13 um have been manufactured and tested. Measurements show competitive results to state-of-the- art mixed signal implementations.

An MPSoC for energy-efficient database query processing

This paper presents a heterogeneous database hardware accelerator MPSoC manufactured in 28 nm SLP CMOS. The 18 mm2 chip integrates a runtime task scheduling unit for energy-efficient query processing and hierarchical power management supported by an ultra-fast dynamic voltage and frequency scaling. Four processing elements, connected by a star-mesh network-on-chip, are accelerated by an instruction set extension tailored to fundamental dataintensive applications. We evaluate the MPSoC with typical database benchmarks focusing on scans and bitmap operations. When the processing elements operate on data stored in local memories, the chip consumes 250 mW and shows a 96x energy efficiency improvement compared to state-of-the-art platforms.

TOWARDS COMPUTATION WITH MICROCHEMOMECHANICAL SYSTEMS

Labs-on-chips are promising candidates for the realization of chemical information systems, where data are embodied in the form of chemical concentrations. In this paper we present the concept of microchemomechanical systems, a lab-on-a-chip technology based on intrinsically active components. The active components are chemical transistors fabricated from phase-changeable polymers that provide a direct feedback mechanism. Therefore this microfluidic platform facilitates the realization of logic operations, if-then structures and the sampling of chemical signals. In analogy with electronic von Neumann CPUs, control and execution unit are integrated on a single chip. Due to the intrinsic activity of the chemical transistors and their small size, microchemomechanical systems are highly suitable for large-scale integration.