Sebastian Pankalla

Design of an organic electronic label on a flexible substrate for temperature sensing

We demonstrate an organic smart label electronic system using p-type organic thin film transistors (OTFT) for temperature sensing applications. The electronic label consists of all organic temperature sensor, memory, logic and interface circuits and detects whether the critical temperature threshold value has been exceeded and records the data digitally in write-once-read-many (WORM) form that can be transmitted to a reader through wireless communication. A comparator is used to interface the sensor to the logic part. The logic circuit block processes and bundles the sensor information along with the necessary additional information that is required for a successful wireless transmission. We have demonstrated the operation of the reported organic smart label system using a silicon based modulator/rectifier circuit for RF communication. The organic logic circuit was built using standard cell design approach with approximately 180 p-type OTFTs. All the circuits were operated with a VDD of -20 V.

Analysis of the mobility of printed organic p-channel transistors depending on the transistor geometry and orientation

The organic thin film transistor (OTFT) is an elementary part of most organic electronic products. A cost efficient and fast way to produce these circuits is by the use of mass printing techniques like flexography or gravure printing. A huge amount of OTFTs is produced via flexography and via spin-coating as a reference. The morphology of the printed layers and the electrical performance of the produced OTFTs are investigated. Based on these investigations, the dependence of the mobility on the transistors source/drain geometry is analysed and explained. Analysed geometry parameters are the transistors channel length, channel width and its orientation compared to printing direction.

Printing technique dependent charge carrier velocity distribution in organic thin film transistors

In this study we investigated the influence of the deposition technique on the surface topology and the resulting device performance in organic thin film transistors (OTFT). We varied the parameters of flexographic and gravure printing for the organic semiconductor (OSC) and did multilayer gravure printing for the dielectric, respectively. Therefore, we manufactured transistors in bottom contact top gate architecture and compared them to spin coated samples. As investigation tool for OTFTs, the charge carrier velocity distribution is correlated with the optical characteristics of the printed layers. We found a dependency of the printing technique on the surface topology of the semiconductor and, due to the resulting increase of the channel length, a broadening of the charge carrier velocity distribution. For the dielectric we found a dependency on the layer thickness which seems to be independent from the deposition technique.

Organic thin-film transistors for circuits in a foundry: process, charge transport phenomena and device library

For the development of circuits consisting of organic thin film transistors (OTFT) with satisfying yield, a stable and reliable process is necessary. This can be achieved by eliminating failure mechanisms and understanding the charge transport phenomena in the individual device. Following the way of a charge through the device, we start with the investigation of the influence of the Schottky barrier height and contact morphology on the device performance by finite-elements simulations. It could be verified that the charge injection limiting contact resistance can be decreased by two orders of magnitude by reducing the thin oxide layer at the source and drain contacts and improving the semiconductor layer morphology at their vicinity. Second, we present an analytical closed-form solution of the OTFT channel potential used for Monte-Carlo charge transport simulations and compute current-voltage and transient response characteristics out of it. In a next step, the influence of the deposition process on the layer interface is investigated. Therefore, velocity distribution measurements of the charge carriers lead to a simulation model with varying disorder, depending on the layer surfaces and deposition techniques. Afterwards, leakage currents through the gate dielectric can be described by a poor conducting semiconductor model in the finite-elements framework. Leakage currents increase power consumption in circuits and, what is more critical, can lead to a total failure of the OTFT. However, they can be influenced by the number of deposited dielectric layers and charge injection supporting self-assembled monolayers at the source and drain contacts. These findings lead to circuit building blocks for an organic device library whereupon still existing performance fluctuations can be coped with Monte-Carlo circuit simulations.

Improved contact resistivity and intra-die variation in organic thin film transistors

We studied the processing-related influence on contact resistivity of organic thin-film transistors in top gate architecture which are placed and oriented differently over flexible substrates. Appropriate plasma treatment reduces degradation of the source and drain contacts, increases effective contact surface for self-assembled monolayer treatment, and thus better injection. Increasing the semiconductor film thickness reduces the contact resistivity until a certain critical thickness. By these means, the contact resistivity has been reduced by two orders of magnitude. We did a mass characterisation of 366 solution-processed transistors on six samples that lead to a modified transfer line method in which we permutated the transistors to extract the contact resistivities. Thus, the intra-die dependency of the contact resistivity on the distance from the centre of the sample, the orientation of the transistor, its width, the pre-processing of the samples and on the semiconductor layer thickness has been ana...