Sebastian Ritz

High level software synthesis for signal processing systems

For the design of complex digital signal processing systems, block diagram oriented simulation has become a widely accepted standard. Current research is concerned with the coupling of heterogenous simulation engines and the transition from simulation to the implementation of digital signal processing systems. Due to the difficulty in mastering complex design spaces high level hardware and software synthesis is becoming increasingly important. The authors concentrate on the block diagram oriented software synthesis of digital signal processing systems for programmable processors, such as digital signal processors (DSP). They present the synthesis environment DESCARTES illustrating novel optimization strategies. Furthermore they discuss goal directed software synthesis, by which code is interactively or automatically generated, which can be adapted to the application specific needs imposed by constraints on memory space, sampling rate or latency.<<ETX>>

Scheduling for optimum data memory compaction in block diagram oriented software synthesis

For the design of complex digital signal processing systems, block diagram oriented synthesis of real time software for programmable target processors has become an important design aid. The synthesis approach discussed in the paper is based on multirate block diagrams with scalable synchronous dataflow (SSDF) semantics. For this class of dataflow graphs the authors present scheduling techniques for optimum data memory compaction. These techniques can be employed to map signals of a block diagram onto a minimum data memory space. In order to formalize the data memory compaction problem, they first derive appropriate implementation measures. Based on these implementation measures it can be shown that optimum data memory compaction consists of optimum scheduling as well as optimum memory allocation. For the class of single appearance (SA) block diagrams with SSDF semantics, scheduling can be reduced to an integer linear programming (ILP) problem. Due to the computational complexity of ILP, the authors also present a suboptimum scheduling selection criterion, which call be used for SA and non SA-schedulers.

Dynamic data flow and control flow in high level DSP code synthesis

The design of todays complex digital signal processing systems, such as communication equipment, increasingly relies on sophisticated CAD tools for block diagram oriented analysis and simulation. Recent work has been concerned with the integration of such simulation tools and those for implementation, i.e. for hardware or software synthesis. Data flow oriented approaches have proven to be very well suited for both tasks due to the nature of most digital signal processing applications. The control of multiple cooperating data flow tasks (including resource management) is an important issue in most digital signal processor (DSP) based systems. This paper describes the integration of control flow into data flow oriented simulation and synthesis. A heterogeneous modeling scheme is proposed. The focus is kept on maintaining the efficiency and simplicity of the data paths while offering additional expressiveness which-as does the data flow paradigm-closely matches the way of thinking of communications system engineers. The usefulness of the novel concepts is demonstrated by a prototype implementation of a digital receiver for wireless data communication.<<ETX>>

High-level software synthesis for the design of communication systems

A synthesis environment that targets software programmable architectures such as digital signal processors (DSPs) is presented. These processors are well suited for implementation of real-time signal processing systems with medium throughput requirements. Techniques that tightly couple the synthesis environment to an existing communication system simulator are also presented. This enables a seamless transition between the simulation and implementation design level of communication systems. Special focus is on optimization techniques for mapping data flow oriented block diagrams onto DSPs. The combination of different mapping and optimization strategies allows comfortable synthesis of real-time code that is highly adapted to application-specific needs imposed by constraints on memory space, sampling rate, or latency. Thus, tradeoff analysis is supported by efficient interactive or automatic exploration of the design space. All presented concepts are illustrated by the design of a phase synchronizer with automatic gain control on a floating-point DSP. >

Retiming of DSP programs for optimum vectorization

Vectorization of digital signal processing programs given in form of data-flow graphs (DFG) is treated. It is shown that for cyclic unit-rate graphs an inherent upper bound on the linear vectorization factor exists. Using the retiming transformation of the original graph this bound can be raised up to a transformation-independent bound which is in general not tight. The authors give a sufficient condition for efficient linear vectorization (vectorization approaching the bound) and propose a corresponding algorithm. As a side result, a useful theorem for retiming of strongly connected graphs is given.<<ETX>>

High performance DSP software using data-flow graph transformations

The paper presents an overview of transformations for DSP programs given in form of coarse-grain data-flow graphs. The goal is to produce a functionally equivalent data-flow graph with improved characteristics, regarding modeling and/or implementation of DSP software. Retiming, unfolding, vectorization, clustering as well as node/arc set extensions are discussed. As an example, an application of the presented transformations to the design of a satellite receiver is presented.<<ETX>>

Fine grain code synthesis within a block diagram oriented code generation environment

Code generation for a system specified by a block diagram facilitates the fast and efficient evaluation of the design space. As a drawback, automatically generated code includes a certain amount of data management overhead compared to handwritten code, especially When the block diagram includes fine granular structures. The authors present a strategy how to overcome certain types of overhead by introducing a novel code generation approach. While traditional tools are based on a one-to-one correspondence between a block on the block diagram level and a functional kernel on the code synthesis level, one new functional kernel for a group of blocks is generated automatically. Doing so, a maximum of dataflow information available from the block diagram level is employed to organize the kernel in an efficient way, having a regard to the designers criterion. As a result, reduction in memory consumption and an increased throughput can be achieved jointly.

A novel approach to the integration of simulation and implementation to digital signal processing systems

Integrating the simulation and implementation of complex digital signal processing systems based on block diagram oriented simulation and code generation is described. The basic concept consists of a generic, i.e., reusable, block diagram with different underlying semantics. This allows the generation of software adapted to the special needs of both simulation and implementation. In order to achieve application-specific implementations, the code generator supports tradeoffs between implementation constraints such as code size, throughput, or latency. Therefore, a wide spectrum of different optimization strategies has been incorporated in the code generator.<<ETX>>

Hierarchization of a priori defined dataflow subgraphs

DSP algorithms are frequently represented by dataflow graphs. These graphs serve as an abstract input specification for an implementation, either in software or hardware. While doing so, the transformation process might require a special treatment of specific subgraphs within the complete dataflow graph. A hierarchization of a subgraph appears as a replacement of the subgraph by a single vertex, representing the same functionality. The subgraph to be hierarchized might be defined by the designer manually or identified automatically, matching certain criterions. Because of the possibility of introducing a deadlock, not every hierarchization is valid. This paper presents an approach that allows to identity such deadlocking subgraphs. If an a priori defined subgraph is identified to result in a deadlock, a concept is presented that allows one to separate the subgraph into sub-subgraphs of maximum size. This allows to apply the special treatment to these sub-subgraphs and not to cancel it completely.