Sebastian Siegel

Optimization of reconfiguration overhead by algorithmic transformations and hardware matching

In this paper we present a method to optimize the overhead in dynamically reconfigurable computing systems. Applications are considered to be partitioned into algorithmic blocks. Our method allows a reduction of overhead when reconfiguration between those blocks is required. For each block a variety of specifications is constructed using high level algorithmic transformations based on a partitioning method for nested loop programs. The partitioning method allows an efficient verification with the given design constraints. The specifications differ in resource usage and execution time. The reconfiguration costs are reduced by finding the best matching specifications of the algorithmic blocks. The specifications with the lowest reconfiguration cost are selected for implementation using the matching information as input for the implementation tools. Finally we present an optimal solution for a reconfigurable 2D mean filter. Two configurations with different filter sizes and word-widths were implemented according to the matching specifications. We reduced the required logic area compared to the non-reconfigurable implementation and reduced significantly the reconfiguration costs.

Algorithm Partitioning including Optimized Data-Reuse for Processor Arrays

This paper describes a method for algorithm partitioning through which affine indexed algorithms are transformed to Processor Arrays. Former design flows start with a spacetime transformation which we omit completely. Therefore, we are able to consider the constraints of a target architecture at the beginning of our design flow. We show our method for three different partitioning schemes and emphasize on the derivation of a schedule. The principle of an optimized data-reuse is introduced for our partitioning methodology. Under this aspect, we give a parameterized Processor Array for the 2D FIR filter algorithm.

Optimized data-reuse in processor arrays

We present a method for co-partitioning affine indexed algorithms resulting in a processor array with an optimized data-reuse. Through this method, a memory hierarchy with an optimized data transfer is derived which allows a significant reduction of the power consumption caused by memory accesses. Apart from former design flows which begin with a space-time transformation, we start with the co-partitioning of the iteration space. This allows an adaption of the resulting processor array towards the constraints of the target architecture at the beginning of the design. We illustrate our method for the full search motion estimation algorithm which bears a high potential of data-reuse.

Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy

In the process of mapping compute-intensive algorithms onto arrays of processing elements (PEs) an efficient usage of channels between PEs and registers within PEs is crucial for achieving a significant algorithm acceleration. In this paper this problem is solved for algorithms represented as systems of uniform recurrence equations. We address an optimization problem in order to realize the algorithmic data dependencies within the processor array (PA) with minimum cost for channels and registers. There, we use a new mapping approach which allows a direct mapping of the algorithm onto the PA by a partitioning method. In contrast to existing approaches, we consider the issue of avoiding redundant usage of channels and registers, which can appear if one instance of a variable has to be transferred from a source PE to several sink PEs. Further, a solution of the optimization problem determines the schedule for the transfer of the variable instances in the channels and their storage in registers as well as the inner schedule for the operations in the PEs. We illustrate our method on the edge detection algorithm.

Efficient realization of data dependencies in algorithm partitioning under resource constraints

Mapping algorithms to parallel architectures efficiently is very important for a cost-effective design of many modern technical products. In this paper, we present a solution to the problem of efficiently realizing uniform data dependencies on processor arrays. In contrary to existing approaches, we formulate an optimization problem to consider the cost of both: channels and registers. Further, a solution to the optimization problem assigns which channels shall be implemented and it specifies the control for the realization of the uniform data dependencies. We illustrate our method on the edge detection algorithm.

Efficient Realization of the Edge Detection Algorithm on a Processor Array with Parallelism on Two Levels

In this paper we derive an efficient realization of the edge detection algorithm on a target architecture with parallelism on two levels. Our target architecture is a processor array where parallelism is achieved 1) within the processing elements by sub-word parallelism (SWP) and 2) within the processor array by an arrangement of several processing elements. We exploit the parallelism on both levels of our processor array by a parameterized two-level partitioning of the algorithm. To obtain a significant speed-up such partitioning parameters are selected which match the target architecture and require a minimum number of additional instructions for SWP. Through this partitioning communication within the processor array appears to be necessary on a large scale. By a detailed examination, which is automatically performed by integer linear programming, we extract and eliminate redundant communication. Hence, our realization of the edge detection algorithm is efficient in terms of energy consumption caused by communication within the processor array. And we obtain a significant speed-up by exploiting both levels of parallelism

A Parallel Hardware-Software System for Signal Processing Algorithms

This paper presents the implementation of a parallel hardware-software system for several digital signal processing algorithms. Besides the description of the developed hardware components, a main focus is set onto the software part: the implemented driver, libraries and user interfaces. One application of the hardware-software system is the reconstruction of tomographoc images, for which the interaction of the hardware and software parts is illustrated.