Sebastien Barasinski

A 45nm single power supply SRAM supporting low voltage operation down to 0.6V

A 256 Kb SRAM macrocell has been implemented in a 45 nm Low Power CMOS technology. A process and temperature tracking write-assist scheme, a write booster circuit and an adaptive read assist scheme allow low voltage operation down to 0.6 V with a single power supply.

A fully integrated power supply unit for fine grain power management application to embedded Low Voltage SRAMs

In complex embedded applications, optimization and adaptation at run time of both dynamic and leakage power have become an issue at SoC coarse grain. We propose in this paper a fully integrated Power Supply Unit for fine grain DVFS and adaptive leakage control. The proposed PSU offers five power modes and can be easily integrated in any IP unit. The PSU has been implemented and validated in a STMicroelectronics 65 nm technology. Dedicated Low-Voltage SRAMs have been designed to allow full DVFS. Using a Hopping technique, the dynamic power consumption can be reduced by a factor of 35%. Using an Ultra-Cut-Off technique, the static power consumption is strongly reduced in stand-by mode, 18 times better than classical MTCMOS.

Product on-chip process compensation for low power and yield enhancement

This paper aims at introducing a reliable on-chip process compensation flow for industrial integrated systems. Among the integrated process compensation techniques, the main one aims at reducing the supply voltage of fast circuits in order to reduce their power consumption while maintaining the specified operating frequency. The proposed design flow includes efficient methodologies to gather/sort on-chip process data but also post-silicon tuning strategies and validation methods at both design and test steps. Concrete results are introduced in this paper to demonstrate the added value of such a methodology. More precisely, it is shown that its application leads to an overall energy reduction ranging from 10% to 20% on fast chips.