Seh-Woong Jeong

An SoC with 1.3 gtexels/s 3-D graphics full pipeline for consumer applications

A high-speed three-dimensional (3-D) graphics SoC for consumer applications is presented. A 166-MHz 3-D graphics full pipeline engine with performance of 33 Mvertices/s and 1.3Gtexels/s, and 333-MHz ARM11 RISC processor, and video composition IPs are integrated together on a single chip. The geometry part of 3-D graphics IP provides full programmability in vertex and triangle level, and two-level multi-texturing with trilinear MIPMAP filtering are realized in the rasterization part. Per-pixel effects such as fog effects, alpha blending, and stencil test are also implemented in the proposed 3-D graphics IP. The rasterization architecture is designed for reducing external memory accesses to achieve the peak performance. The chip is fabricated using 0.13/spl mu/m CMOS technology and its area is 7.1/spl times/7.0mm/sup 2/.

A Low Power TLB Structure for Embedded Systems

We present a new two-level TLB (translationlook-aside buffer) architecture that integrates a 2-waybanked filter TLB with a 2-way banked main TLB. Theobjective is to reduce power consumption in embeddedprocessors by distributing the accesses to TLB entriesacross the banks in a balanced manner. First, an advancedfiltering technique is devised to reduce access power byadopting a sub-bank structure. Second, a bank-associativestructure is applied to each level of the TLB hierarchy.Simulation results show that the Energy*Delay productcan be reduced by about 40.9% compared to a fullyassociativeTLB, 24.9% compared to a micro-TLB with4+32 entries, and 12.18% compared to a micro-TLB with16+32 entries.

In-network reorder buffer to improve overall NoC performance while resolving the in-order requirement problem

Data-intensive functions on chip, e.g., codec, 3D graphics, pixel processing, etc. need to make best use of the increased bandwidth of multiple memories enabled by 3D die stacking via accessing multiple memories in parallel. Parallel memory accesses with originally in-order requirements necessitate reorder buffers to avoid deadlock. Reorder buffers are expensive in terms of area and power consumption. In addition, conventional reorder buffers suffer from a problem of low resource utilization. In our work, we present a novel idea, called in-network reorder buffer, to increase the utilization of reorder buffer resource. In our method, we move the reorder buffer resource and related functions from network entry/exit points to network routers. Thus, the in-network reorder buffers can be better utilized in two ways. First, they can be utilized by other packets without in-order requirements while there are no in-order packets. Second, even in-order packets can benefit from in-network reorder buffers by enjoying more shares of reorder buffers than before. Such an increase in reorder buffer utilization enables NoC performance improvement while supporting the original in-order requirements. Experimental results with an industrial strength DTV SoC example show that the presented idea improves the total execution cycle by 16.9%.

A banked-promotion TLB for high performance and low power

This research is to design a simple but high performance TLB (translation lookaside buffer) system with low power consumption. Thus, we propose a new TLB structure supporting two page sizes dynamically and selectively for high performance and low cost design without any operating system support. For high performance, a promotion-TLB is designed by supporting two page sizes. Also in order to attain low power consumption, a banked-TLB is constructed by dividing one fully associative TLB space into two sub fully associative TLBs. These two structures are integrated to form a banked-promotion TLB as a low power and high performance TLB structure for embedded processors. According to the results of comparison and analysis, a similar performance can be achieved by using fewer TLB entries and also energy dissipation can be reduced by around 50% compared with the fully associative TLB.

An SoC with 1.3 Gtexels/s 3D graphics full pipeline engine for consumer applications

A 3D graphics SoC whose performance is 33 Mvertices/s and 1.3 Gtexels/s is designed for consumer applications. The SoC integrates an ARM11 RISC processor, a dedicated 3D graphics full pipeline engine, and video composition IPs. The SoC contains 17.9 M transistors in 50 mm/sup 2/ area and is fabricated in a 0.13 /spl mu/m 7M CMOS process.

A banked-promotion translation lookaside buffer system

We present a simple but high performance translation lookaside buffer (TLB) system with low power consumption for use in embedded systems. Our TLB structure supports two page sizes dynamically and selectively to achieve high performance with low hardware cost. To minimize power consumption, a banked-TLB is constructed by dividing one fully associative (FA) TLB space into two separate FA TLBs. These two structures are integrated to form a banked-promotion (BP) TLB. Promotion overcomes the unbalanced utilization of a banked-TLB by moving adjacent entries out of the primary banks into a separate super-page TLB. Simulation results show that the Energy* Delay product can be reduced by about 99.8%, 19.2%, 24.2%, and 24.4% compared with a FA TLB, a micro-TLB, a banked-TLB, and a victim-TLB respectively. Therefore, the BP TLB offers high performance with low power consumption and low hardware cost.

Efficient random vector verification method for an embedded 32-bit RISC core

Processors require both intensive and extensive functional verification in their design phase to satisfy their general purposability. The proposed random vector verification method for CalmRISC/sup TM/-32 core meets this goal by contributing complementary assistance for conventional verification methods. It adopts a cycle-accurate instruction level simulator as a reference model, runs simulation in both the reference and the target HDL and reports errors if any difference is found between them. These processes are automatically performed in the unified environment. The instruction level simulator, the core part in the verification environment is able to simulate almost every aspect of RISC processors from functional behavior of each opcode to timing details in the pipeline flow in fast speed. Its design style from microprogramming scheme also makes its structure modular and flexible.

A selectively accessing TLB for high performance and lower power consumption

This paper presents a structure of TLB (translation lookaside buffer) for low power consumption but high performance. The proposed TLB is constructed as a combination of one block buffer and two-way banked TLBs. The processor can access the block buffer or one of two banked TLBs selectively. This feature is quite different from that used in the traditional block buffering technique. Simulation results show its effectiveness in terms of power consumption and energy*delay product. The proposed TLB can reduce power consumptions by about 40%, 10%, 23%, and 23%, compared with a FA (fully associative)-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Also the proposed TLB can reduce Energy*Delay products by about 38%, 28%, 21%, and 21%, compared with a FA-TLB, a micro-TLB, a victim-TLB, and a banked-TLB respectively. Therefore the proposed TLB can achieve low power consumption and high performance with a simple architecture.

CalmRISC/sup TM/-32: a 32-bit low-power MCU core

Architecting todays embedded processor core faces several important design challenges: low power, high performance, and system-on-a-chip considerations. Moreover, support for high-level language constructs and operating systems becomes increasingly critical for acceptance to various applications. CalmRISC/sup TM/-32 effectively meets these challenges by incorporating a carefully designed instruction set, an energy-efficient pipeline design, debugging support with trace mode/CalmBreaker/sup TM/ (an in-circuit debugger), and a generic, yet efficient coprocessor interface. Using a 0.25 /spl mu/m static CMOS standard cell library and compiled datapath cells, the first implementation of CalmRISC/sup TM/-32 operates at 130 MHz (under worst conditions) and consumes 150 /spl mu/A/MHz at 2.5 V. This paper presents a brief description of the instruction set, the overall microarchitecture, and the coprocessor interface of CalmRISC/sup TM/-32.

CalmRISC/sup TM/: a low power microcontroller with efficient coprocessor interface

The paper presents the low power architecture of CalmRISC, a low power 8-bit microcontroller consuming only 0.1 mW per MIPS at 3.0 V, and its efficient coprocessor interface. The architectural consideration of CalmRISC for low power consumption is presented. Some low power circuit design schemes, as well as an efficient coprocessor interface scheme in CalmRISC are proposed and discussed.