Sehwan Lee

A lifespan-aware reliability scheme for RAID-based flash storage

Due to the ever-growing capacity of flash memory along with its good properties such as low-power consumption and high performance, flash-based SSDs (solid state disks) are anticipated to be used in the storage of high-end server systems. However, the reliability problem of flash devices is becoming increasingly serious. The number of P/E (program/erase) cycles allowed to each flash block is too small, especially less than 10,000 for MLC (multi-level cell) flash memory. Furthermore, the bit error rate of flash memory becomes rapidly high as the number of P/E cycles increases. To relieve these problems, we present a lifespan-aware reliability scheme, which adopts RAID technologies together with ECCs (error correction codes). First, our scheme dynamically manages the size of striping group to cope with the increasing error rates of flash memory as the number of P/E cycles increases. Second, we use a device-aware log block mapping scheme, which uses different reliability policies for data blocks and log blocks by taking advantage of the characteristics of each block type. Third, we use small amount of storage class memory (SCM) to save parity blocks temporarily. By absorbing frequent updates of parity into SCM, we can extend the lifespan of flash memory. Simulation experiments show that our scheme obtains high reliability with minimum space overhead as well as improved I/O performances compared to traditional RAID-5.

Object-oriented design of main-memory DBMS for real-time applications

Many applications, such as telecommunication, process control, and virtual reality, require real-time access to database. Main-memory DBMS, which becomes feasible with the increasing availability of large and relatively cheap memory, can provide better performance than disk-based systems for real-time applications. This paper presents an overall architecture of M/sup 2/RT, a main-memory real-time DBMS, and an object-oriented design of its storage system called M/sup 2/RTSS. M/sup 2/RTSS provides classes that implement the core functionality of storage management, real-time transaction scheduling, and recovery. Implemetation-specific information is encapsulated in these classes and extensions can be made by inheritance. With object-oriented features, M/sup 2/RTSS can easily incorporate new development in application requirements and the result of ongoing research in real-time systems.

A Demand-Based FTL Scheme Using Dualistic Approach on Data Blocks and Translation Blocks

Using NAND flash memory as a storage device is in the limelight due to its many attractive features, but it also has vulnerable points. Specifically, as NAND flash memory does not allow the overwrite of data in the same place, it performs out-place-update, which requires the address translation table between logical and physical addresses. Due to the ever growing size of NAND flash memory, keeping the whole address translation table in SRAM is becoming increasingly a serious problem. In this paper, we present three management schemes to reduce the SRAM space in address translation but also guarantee the performance. First, we store data in NAND flash memory by using a page level mapping scheme. A page level mapping scheme allows NAND flash memory to store data in any place, and thus we can improve the storage efficiency. Second, we keep only a small amount of address translation entries in the page address translation cache (PATC) to reduce the size of SRAM. The other address translation entries that are in NAND flash memory will be loaded in SRAM on demand. Furthermore, we manage an address translation table in NAND flash memory by using a hybrid mapping scheme to reduce the size of translation block mapping directory (TBMD). Third, we take advantage of PATC to identify data whether they are hot or cold. By separating hot data from cold data using PATC, we prolong NAND flash memorys lifespan and reduce garbage collection time without any additional cost. Integrating these three schemes leads to the improved read response time compared to the state-of-the-art FTL algorithm, DFTL, by up to 56.9% though it uses only 10% of SRAM. Moreover, if the proposed scheme uses the same amount of SRAM, the response time is improved and the average number of valid pages in a victim block also decreases by up to 67% by efficiently separating hot data from cold data.

Improving the Demand Paging Performance with NAND-type Flash Memory

Because of its superior read performance and other favorable features over standard NAND flash memory, OneNAND flash has become the most promising alternative for implementing high-performance mobile devices. However, the superior read performance of OneNAND flash can not be fully utilized under the I/O architecture of existing general purpose operating systems. This paper investigates the problem in the context of demand paging, and introduces a new scheme called virtual I/O segment for solving that problem. Experiments by implementation show that the read latency of OneNAND flash based block device can be reduced as much as 54% by the use of virtual I/O segments. Also, page fault handling time of real-world embedded applications is reduced as much as 42%.

Unifying Buffer Replacement and Prefetching with Data Migration for Heterogeneous Storage Devices

With the good properties of NAND flash memory such as small size, shock resistance, and low-power consumption, large capacity SSD (Solid State Disk) is anticipated to replace hard disk in high-end systems. However, the cost of NAND flash memory is still high to substitute for hard disk entirely. Using hard disk and NAND flash memory together as secondary storage is an alternative solution to provide relatively low response time, large capacity, and reasonable cost. In this paper, we present a new buffer cache management scheme with data migration that is optimized to use both NAND flash memory and hard disk together as secondary storage. The proposed scheme has three salient features. First, it detects I/O access patterns from each storage, and allocates the buffer cache space for each pattern by computing marginal gain adaptively considering the I/O cost of storage. Second, it prefetches data selectively according to their access pattern and storage devices. Third, it moves the evicted data from the buffer cache to hard disk or NAND flash memory considering the access patterns of block references on the reclamation. Trace-driven simulations show that the proposed scheme improves the I/O performance significantly. It enhances the buffer cache hit ratio by up to 29.9% and reduces the total I/O elapsed time by up to 49.5% compared to the well-acknowledged UBM scheme.

Vector Read: Exploiting the Read Performance of Hybrid NAND Flash

OneNAND flash is a NAND based hybrid flash memory which offers much better read/write performance and other functionalities than standard NAND flash memory. Because of its superior read performance, OneNAND flash became the most promising storage solution for implementing high performance mobile device which adopts demand paging memory architecture. However, unfortunately, existing general purpose operating systems, such as Linux, fail to exploit the read performance of OneNAND flash because of a restriction imposed by their I/O architecture and device driver interface. This paper investigated the cause of such inability, and proposed the design of vectored read scheme for solving that problem. Implementation studies on Linux kernel shows that vectored read scheme reduces the block level read latency of OneNAND flash by up to 41% compared with commercial FTL device. It also proved its effectiveness in real-world applications by reducing page fault handling time by 28%.

An extensible architecture for main-memory real-time storage systems

M/sup 2/ RTSS is a main-memory storage system, which has been under recent development at Seoul National University as a vehicle for high-performance and real-time database application research. To deal with requirements from various applications, M/sup 2/ RTSS architecture is designed to have extensibility in many aspects of storage system functionality. One crucial aspect of such extensibility is that the user is allowed to compose application-specific, high-level operations with a basic set of operations supplied by the system. Called composite actions in M/sup 2/ RTSS, these operations run on a customized M/sup 2/ RTSS server with minimum interprocess communication with user processes, thus increasing the overall performance of executing user transactions. The object-oriented design and implementation of the whole M/sup 2/ RTSS system facilitates this type of application-specific extension as well as other types in transaction scheduling and recovery. This paper first describes the overall architecture of M/sup 2/ RTSS and then explores the composition of application-specific operations in detail.

Memory-efficient compressed filesystem architecture for NAND flash-based embedded systems

Cost-effectiveness is one of the most critical factors in the development of low-end embedded systems. The use of a compressed filesystem is a simple but effective solution for achieving such cost-effectiveness. However, since conventional compressed filesystems are designed for disk-like devices and relatively abundant computing resources, they are not suitable for low-end embedded systems with small amount of memory and NAND flash-based storage. This paper presents a memory-efficient compressed filesystem designed for low-end embedded systems and NAND flash memory. Experiments by prototype implementation show that the proposed filesystem outperforms conventional ones in terms of memory-efficiency and I/O performance.

Selective Context Switching on Flash Memory

Flash memory prevails as a mobile storage device because it offers a fast read access time and better shock resistance compared to a hard disk. However, generic operating systems such as Linux do not take advantages of the hardware performance of flash memory because they do not change the architectures which are optimized for hard disks. The existing operation systems switch contexts to handle requests upon every device activation. If Linux switches contexts with every request when using hard disks as storage devices,the context switching time is not burdened compared to its total I/O time. However, in the event that Linux uses flash memory as a storage device, the context switching time becomes greatly burdened due to its fast access time. This paper improves the context switching scheme by reducing the amount of unnecessary context switching. As a result,an overall performance increase of 5% is gained regardless of the workloads.