Hyokyung Bahn

A flash compression layer for SmartMedia card systems

Flash memory based SmartMedia card is becoming increasingly popular as data storage for mobile consumer electronics. Since flash memory is an order of magnitude more expensive than magnetic disks, data compression can be effectively used in managing flash memory based storage systems. However, compressed data management in flash memory is challenging because it only supports page-based I/Os. For example, when the size of compressed data is smaller than the page size, internal fragmentation occurs and this degrades the effectiveness of compression seriously. In this paper, we developed a flash compression layer (FCL) for the SmartMedia card systems. FCL stores several small compressed pages into one physical page by using a write buffer. Based on prototype implementation and simulation studies, we show that the proposed system offers the storage of flash memory more than 140% of its original size and expands the write bandwidth significantly.

CLOCK-DWF: A Write-History-Aware Page Replacement Algorithm for Hybrid PCM and DRAM Memory Architectures

Phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy of future computer systems. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6-10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM have been suggested. In this paper, we present a new memory management technique for hybrid PCM and DRAM memory architecture that efficiently hides the slow write performance of PCM. Specifically, we aim to estimate future write references accurately and then absorb frequent memory writes into DRAM. To do this, we analyze the characteristics of memory write references and find two noticeable phenomena. First, using write history alone performs better than using both read and write history in estimating future write references. Second, the frequency characteristic is a better estimator than temporal locality in predicting future memory writes. Based on these two observations, we present a new page replacement algorithm called CLOCK-DWF (CLOCK with Dirty bits and Write Frequency) that significantly reduces the number of write operations that occur on PCM and also increases the lifespan of PCM memory.

An energy-efficient sensor routing scheme for home automation networks

In the emerging ubiquitous home, sensors are placed everywhere in the house and collect various physical data such as temperature, humidity, and light to provide information to consumer electronics devices. The devices are then automatically activated if necessary. For example, the ventilator works when the air is foul and the heating system performs according to the weather and the existence of people in the house. Because sensors have limited battery power, energy-efficient routing is important. In this paper, we present a new sensor routing scheme that provides energy-efficient data delivery from sensors to the home base station. The proposed scheme divides the home area into sectors and locates a manager node to each sector. The manager node receives collected data from sensors and delivers the data to the base station through the shortest path of the 2-dimensional (x, y) coordinates. Performance results show that the proposed scheme reduces energy consumption significantly compared with conventional sensor routing schemes.

Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory

In order to reduce the energy dissipation in main memory of computer systems, phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6-10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM memory have been suggested. In this paper, we present a new memory management technique for hybrid PCM and DRAM memory architecture that efficiently hides the slow write performance of PCM. Specifically, we aim to estimate future write references accurately and then absorb most memory writes into DRAM. To do this, we analyze the characteristics of memory write references and find two noticeable phenomena. First, using write history alone performs better than using both read and write history in estimating future write references. Second, the frequency characteristic is a better estimator than temporal locality but combining these two properties appropriately leads to even better results. Based on these two observations, we present a new page replacement algorithm called CLOCK-DWF (CLOCK with Dirty bits and Write Frequency) that significantly reduces the number of write operations that occur on PCM.

Secure user identification for consumer electronics devices

With the evolution of consumer electronics technologies, personal information in consumer devices is becoming increasingly valuable. To protect private information from misuses due to loss or theft, secure user identification mechanisms should be equipped into the consumer devices. This paper develops a secure user identification system for consumer electronics devices based on fingerprint identification. The fingerprint identification system is one of the biometric sensor technologies, which provides high accuracy and convenience than other identification techniques. Specifically, the proposed system uses the orientation map and the edit-distance for immediate and accurate identification of users. Experimental results show that the proposed system achieves good performance in terms of the false rejection rate and the false acceptance rate.

A lifespan-aware reliability scheme for RAID-based flash storage

Due to the ever-growing capacity of flash memory along with its good properties such as low-power consumption and high performance, flash-based SSDs (solid state disks) are anticipated to be used in the storage of high-end server systems. However, the reliability problem of flash devices is becoming increasingly serious. The number of P/E (program/erase) cycles allowed to each flash block is too small, especially less than 10,000 for MLC (multi-level cell) flash memory. Furthermore, the bit error rate of flash memory becomes rapidly high as the number of P/E cycles increases. To relieve these problems, we present a lifespan-aware reliability scheme, which adopts RAID technologies together with ECCs (error correction codes). First, our scheme dynamically manages the size of striping group to cope with the increasing error rates of flash memory as the number of P/E cycles increases. Second, we use a device-aware log block mapping scheme, which uses different reliability policies for data blocks and log blocks by taking advantage of the characteristics of each block type. Third, we use small amount of storage class memory (SCM) to save parity blocks temporarily. By absorbing frequent updates of parity into SCM, we can extend the lifespan of flash memory. Simulation experiments show that our scheme obtains high reliability with minimum space overhead as well as improved I/O performances compared to traditional RAID-5.

Shortcut-JFS: A write efficient journaling file system for phase change memory

Journaling file systems are widely used in modern computer systems as it provides high reliability with reasonable performance. However, existing journaling file systems are not efficient for emerging PCM (Phase Change Memory) storage. Specifically, a large amount of write operations performed by journaling incur serious performance degradation of PCM storage as it has long write latency. In this paper, we present a new journaling file system for PCM, called Shortcut-JFS, that reduces write amount of journaling by more than a half exploiting the byte-accessibility of PCM. Specifically, Shortcut-JFS performs two novel schemes, 1) differential logging that performs journaling only for modified bytes and 2) in-place checkpointing that removes unnecessary block copy overhead. We implemented Shortcut-JFS on Linux 2.6, and measured the performance of Shortcut-JFS and legacy journaling schemes used in ext 3. The results show that the performance improvement of Shortcut-JFS against ext 3 is 40% on average.

FeGC: An efficient garbage collection scheme for flash memory based storage systems

NAND flash memory is a promising storage media that provides low-power consumption, high density, high performance, and shock resistance. Due to these versatile features, NAND flash memory is anticipated to be used as storage in enterprise-scale systems as well as small embedded devices. However, unlike traditional hard disks, flash memory should perform garbage collection that consists of a series of erase operations. The erase operation is time-consuming and it usually degrades the performance of storage systems seriously. Moreover, the number of erase operations allowed to each flash memory block is limited. This paper presents a new garbage collection scheme for flash memory based storage systems that focuses on reducing garbage collection overhead, and improving the endurance of flash memory. The scheme also reduces the energy consumption of storage systems significantly. Trace-driven simulations show that the proposed scheme performs better than various existing garbage collection schemes in terms of the garbage collection time, the number of erase operations, the energy consumption, and the endurance of flash memory.

P/PA-SPTF: Parallelism-aware request scheduling algorithms for MEMS-based storage devices

MEMS-based storage is foreseen as a promising storage media that provides high-bandwidth, low-power consumption, high-density, and low cost. Due to these versatile features, MEMS storage is anticipated to be used for a wide range of applications from storage for small handheld devices to high capacity mass storage servers. However, MEMS storage has vastly different physical characteristics compared to a traditional disk. First, MEMS storage has thousands of heads that can be activated simultaneously. Second, the media of MEMS storage is a square structure which is different from the platter structure of disks. This article presents a new request scheduling algorithm for MEMS storage called P-SPTF that makes use of the aforementioned characteristics. P-SPTF considers the parallelism of MEMS storage as well as the seek time of requests on the two dimensional square structure. We then present another algorithm called PA-SPTF that considers the aging factor so that starvation resistance is improved. Simulation studies show that PA-SPTF improves the performance of MEMS storage by up to 39.2% in terms of the average response time and 62.4% in terms of starvation resistance compared to the widely acknowledged SPTF algorithm. We also show that there exists a spectrum of scheduling algorithms that subsumes both the P-SPTF and PA-SPTF algorithms.

Personalized recommendation schemes for DTV channel selectors

The emergence of new TV media such as digital cable and satellite has diversified TV contents. This makes the task of finding ones favorite contents among hundreds of TV channels a time consuming job. To relieve this channel selection overhead, this paper presents personalized recommendation schemes for DTV channel selectors. The proposed recommendation schemes analyze each persons previous watching behavior in terms of recency and frequency, and then utilize this information in the control of the top-down channel selector. Simulation studies show that the proposed schemes reduce the seek cost of the DTV channel selector by up to 62.8% for the trace set we considered