Seigo Kotani

Josephson modified variable threshold logic gates for use in ultra-high-speed LSI

A gate family called modified variable threshold logic (MVTL) is proposed. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, an operating margin of +or-43% and a switching speed of 2.5 ps/gate are obtained. the gate area is 30 mu m*24 mu m with a 1.5- mu m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit*16-bit multiplier, and a 16-bit arithmetic logic unit have been successfully operated. When the Josephson gate is operated with three-phase power, it is possible to construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplies. >

Josephson 8-bit shift register

A Josephson 8-bit shift register for use in Josephson computers and signal processors is described. The gates used in the circuit are modified variable threshold logic (MVTL) gates fabricated by 2.5-/spl mu/m Nb/AlO/SUB x//Nb junction technology with Mo resistors and SiO/SUB 2/ insulation. They are driven by a three-phase power supply. The shift register has 112 gates and occupies a 1.1/spl times/2.1-mm/SUP 2/ area. Correct shift, load, hold, and clear operations were experimentally confirmed for all bits. The circuit operated at a clock frequency up to 2.3 GHz. Its power consumption was 1.8 mW. This power level is two or three orders of magnitude lower than for Si or GaAs shift registers.

A 1.5-ps Josephson OR gate

A high-speed performance of a Josephson MVTL (modified variable threshold logic) OR gate was demonstrated. This fast operation was achieved by miniaturizing the gate. An MVTL gate fabricated with Nb/AlO/sub x//Nb Josephson junctions, SiO/sub 2/ insulators and Mo resistors is shown. The Josephson critical current, I/sub c/, is proportional to the junction size, so when the size is reduced, the increased I/sub c/ spread is crucial in operating many junctions at the same bias current. The maximum-to-minimum spread in I/sub c/ for 100 gates connected in series was +or-6% of the mean. This small spread was achieved by reducing the thickness of the upper Nb electrode of the electron junction from 90 nm to 60 nm. The average current of I/sub c/ was 8800 A/cm/sup 2/, and the measured operating margin of a single gate was +or-32%. At the highest bias level, the average gate delay was 1.5 ps/gate.<<ETX>>

9 ps Gate Delay Josephson OR Gate with Modified Variable Threshold Logic

A Josephson logic OR gate suitable for high speed logic circuits is proposed and tested. This gate has a structure modified from Variable Threshold Logic (VTL) to obtain large operating margin and small occupation area. The operating margin is calculated as ±19% for fan-out of 2, even with the critical current variation of ±20%. The circuit area is 40×60 µm2. A chain of 5-stage OR gates was fabricated. The gates had Josephson junctions of 4 µm and 7 µm diameter made with Pb-alloy technology. The minimum gate delay of 9 ps was measured using a Josephson sampler.

TrustCube: An Infrastructure that Builds Trust in Client

In a client-server environment, typically a lot of sensitive data and/or processes (for clients as well as for the server) are maintained at the server. In order to protect the integrity of the server and prevent leakage of data to unauthorized entities, it is important to make sure that only the authorized person with properly configured authorized platforms can gain the access to the server.

High-speed Josephson processor technology

High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.

Feasibility of an ultra-high-speed Josephson multiplier

The authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all-niobium junctions. They designed a 16-bit /spl times/ 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) OR-gates and single-junction AND gates. These gates consisted of Nb/AlO/SUB x//Nb Josephson junctions, Nb wiring, Mo resistors, and SiO/SUB 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 /spl mu/m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wiring was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra high-speed multiplier, about five times faster than any semiconductor device.

A subnanosecond clock Josephson 4-bit processor

A Josephson 4-b processor with a 4-bit slice microprocessor, a 4-b multiplier, a 12-b accumulator, an 8-kb ROM, and a sequencer is described. The chip was fabricated with 1.5- mu m all-niobium technology, and contains 24000 Nb/AlO/sub x//Nb Josephson junctions. The processor was designed using a bit slice structure and a simple ripple-carry method, and it has a data sequence based on a three-stage pipeline. Experiments confirmed that the processor functions operated correctly. The critical path measurements for each stage show that the ROM has a 100-ps access time, the microprocessor can be clocked at 1.1 GHz, and the multiplier has a 200-ps multiplication time. The power dissipation of the chip was 6.1 mW. >

Ultrahigh-speed logic gate family with Nb/Al-AlO x /Nb Josephson junctions

The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlOx/Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.

5.6 ps Gate Delay All Refractory Josephson OR Gate with Modified Variable Threshold Logic

The modified variable threshold logic (MVTL) OR gate has a wide operating margin of ±43% and occupies a small area of 45×65 µm2. We made this gate with all refractory material including Nb/Al-AlOx/Nb junctions and Mo resistors. A chain of 5-stage MVTL OR gate was fabricated. The junction diameters were 4 µm and 7 µm, and critical current density was 1400 A/cm2. The minimum gate delay of 5.6 ps/gate was measured using a Josephson sampler.