N. Fujimaki

A single-chip SQUID magnetometer

A superconducting quantum interference device (SQUID) magnetometer in which all components are integrated on a single chip is discussed. The chip includes a feedback circuit, a pickup coil, and a SQUID sensor. The feedback circuit consists of a superconducting storage loop and a WRITE gate. The chip, fabricated with Nb/AlO/sub x//Nb Josephson junctions, Mo resistors and SiO/sub 2/ insulation. The sensitivity is 7*10/sup -5/ Phi /sub 0// square root Hz for the flux in the SQUID sensor and 4.5*10/sup -9/ T/m square root Hz for the magnetic field gradient at the pickup coil. This sensitivity is limited by environmental noise and can be increased with shielding. The device is useful for the construction of a magnetometer array for biomagnetic image sensing. >

A 4K Josephson memory

The authors describe the design and experimental performance of a 4 K*1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlO/sub x//Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW. >

Josephson modified variable threshold logic gates for use in ultra-high-speed LSI

A gate family called modified variable threshold logic (MVTL) is proposed. The OR gate is a two-junction interferometer with one magnetically coupled control line. Magnetic coupling and current injection are used to switch the logic state of the gate. By optimizing the gate parameters, an operating margin of +or-43% and a switching speed of 2.5 ps/gate are obtained. the gate area is 30 mu m*24 mu m with a 1.5- mu m minimum junction diameter. The gate family consists of an OR gate, a single-junction AND gate, and a timed inverter (TI) that consists of the OR gate, a junction, and resistors. The delay time of the gate operated in the actual circuit was found to be less than 10 ps. Circuits having up to 1000 gates, the critical path model of a 16-bit*16-bit multiplier, and a 16-bit arithmetic logic unit have been successfully operated. When the Josephson gate is operated with three-phase power, it is possible to construct any sequential circuit without the complex latch circuit required to prevent the race condition for one- or two-phase power supplies. >

Magnetoencephalographic study on the cerebral neural activities related to the processing of visually presented characters

Neuromagnetic fields were recorded from normal subjects to study the time course of cerebral neural activation while they performed a matching task of visual stimuli in which sequentially presented Japanese characters or unreadable pseudo-characters were compared according to phonological (reading of the characters) or graphical (geometry of the pseudo-characters) identity. In response to the single real-character or pseudo-character which was presented the latest distinct magnetic field components were observed, from which current dipole sources of the fields were localized in the individual magnetic resonance images of the brain. In the phonological identification, the sources were found in the parieto-occipital extrastriate cortex at 155-210 ms following the character presentation, and in the posterior temporal region (part of the Wernickes area) and the posterior superior temporal region of the visual/auditory association cortex at 210-410 ms. The activity in these temporal regions was left hemisphere dominant, and may be the neural basis of phonological processing of the visual characters. In the graphical identification, sources occurring at 125-250 ms were noted in the inferior temporo-occipital region, and those at 180-460 ms in the posterior temporal and posterior superior temporal regions of the right hemisphere. These results indicate that the activities in the temporal area are lateralized to the left for the phonological processing and to the right for the graphical processing.

Josephson 8-bit shift register

A Josephson 8-bit shift register for use in Josephson computers and signal processors is described. The gates used in the circuit are modified variable threshold logic (MVTL) gates fabricated by 2.5-/spl mu/m Nb/AlO/SUB x//Nb junction technology with Mo resistors and SiO/SUB 2/ insulation. They are driven by a three-phase power supply. The shift register has 112 gates and occupies a 1.1/spl times/2.1-mm/SUP 2/ area. Correct shift, load, hold, and clear operations were experimentally confirmed for all bits. The circuit operated at a clock frequency up to 2.3 GHz. Its power consumption was 1.8 mW. This power level is two or three orders of magnitude lower than for Si or GaAs shift registers.

High-speed Josephson processor technology

High-speed operation of Josephson processors is demonstrated. They are a 4-b microprocessor, a 4-b processor, and an 8-b digital signal processor. Key technologies to realize these circuits are described from the viewpoint of circuit design. The technologies are a high-speed logic gate, named MVTL (modified variable threshold logic), and a three-phase sinusoidal power supply system. The MVTL gate has a large operating margin and high sensitivity. The MVTL gate family consists of OR, AND, 2/3 majority (MJ), and timed inverter (TI). Using these gates a variety of processors have been designed. These processors operate with three-phase power. The waveform is sinusoidal with DC-offset. This power supply system needs no latch and regulator circuit. This makes the processor very simple, and thus results in high-speed operation. To fabricate these processors, niobium junctions are very important, because they are reliable, uniform, controllable, and reproducible. High-speed gates, three-phase power supplies, and niobium junctions are indispensable for high-speed Josephson processors.

Feasibility of an ultra-high-speed Josephson multiplier

The authors discuss the design, fabrication, and evaluation of a Josephson multiplier model featuring all-niobium junctions. They designed a 16-bit /spl times/ 16-bit parallel multiplier and fabricated its critical path model consisting of 828 gates. The circuit was designed using modified variable threshold logic (MVTL) OR-gates and single-junction AND gates. These gates consisted of Nb/AlO/SUB x//Nb Josephson junctions, Nb wiring, Mo resistors, and SiO/SUB 2/ insulators. Both the minimum linewidth and junction diameter were 2.5 /spl mu/m. The observed multiplication time using the critical path model was 1.1 ns. The propagation delay due to the interconnecting wiring was estimated to be 0.20 ns, and the longest path of the circuit consisted of 103 gates. Thus the average gate delay in the circuit was estimated to be 8.7 ps/gate. These results point to the possibility of an ultra high-speed multiplier, about five times faster than any semiconductor device.

Josephson pseudorandom bit-sequence generator

A nine-bit Josephson pseudorandom bit-sequence generator for use in Josephson computers and signal processors is described. The gates used in the circuit are modified variable threshold logic (MVTL) gates fabricated using 2.5- mu m Nb-AlO/sub x/-Nb junction technology with Mo resistors and SiO/sub 2/ insulation. They are driven by a three-phase power supply. The circuit consists of 66 gates and its area is 4.2*0.5 mm/sup 2/. Correct bit sequences with one period of 2/sup 9/-1=511 clocks were obtained. Its power consumption was 0.9 mW. The circuit operated at a clock frequency of up to 2.2 GHz. >

Ultrahigh-speed logic gate family with Nb/Al-AlO x /Nb Josephson junctions

The modified variable threshold logic (MVTL) OR gate has a wide operating margin and occupies a small area, so that a gate family using this OR gate is suitable for LSI logic circuits. This paper describes the design, fabrication process, and evaluation of the MVTL gate family. The gate family is composed of OR, AND, and 2/3 MAJORITY gates. The gates were made with all refractory material including Nb/ Al-AlOx/Nb junctions and Mo resistors, and they were patterned by using a reactive ion etching (RIE) technique. The logic delay of the gate was measured with a Josephson sampler. The minimum delays for OR, AND, and 2/3 MAJORITY gates were 5.6, 16, and 21 ps/gate, respectively.

A subnanosecond Josephson 16-bit ALU

The design and characteristics of a Nb based Josephson 16-bit arithmetic logic unit (ALU) for use as a major component of a practical Josephson microprocessor are discussed. The ALU has 900 gates and uses dual-rail logic to perform 12 functions. One of the simplest algorithms, the ripple-carry method, is used. Experiments confirmed that ALU functions operated correctly. The critical path delay time was 860 ps for a 10.1-mW power dissipation. Average values estimated from experiments are 9.2 ps for the gate delay and 113 mu W for the gate power dissipation. The results demonstrate that development of a Josephson microprocessor is feasible. >