Seiichiro Yamaguchi

On the accuracy and efficiency of substrate current calculations for sub-μm n-MOSFET's

The accuracy and efficiency of the self-consistent (regarding the electric field) Monte Carlo model, nonself-consistent Monte Carlo model, and the soft-threshold lucky electron model (LEM) for the calculation of substrate currents in deep sub-/spl mu/m n-MOSFETs are investigated. While the two Monte Carlo models are in good agreement with the experiment, the simpler LEM model still gives reasonable results even for a 0.16 /spl mu/m n-MOSFET. On the other hand, huge differences in the CPU time consumption are found and the LEM is about four orders of magnitude faster than the self-consistent Monte Carlo simulations. The nonself-consistent calculations are only one order of magnitude slower than the LEM. The good agreement with the experiment is obtained without considering the so-called surface impact ionization or any fitting of parameters on the device level.

Convergence estimation for stationary ensemble Monte Carlo simulations

A criterion for the convergence of the stochastic Monte Carlo simulations is necessary to ensure the reliability of their results and to guarantee efficiency. Due to the finite scattering rate in Monte Carlo simulations all quantities are in general correlated in time. This makes the estimation of the stochastic error of the sampled statistics difficult. In this work the theoretical basis of a method found in literature is explored which allows to calculate the stochastic error of stationary Ensemble Monte Carlo simulations and which requires only a rough estimate of the magnitude of the largest correlation time of the sampled quantities. The feasibility of the method is demonstrated by application to substrate current calculations for nMOSFETs.

Inverse Modeling as a Basis for Predictive Device Simulation of Deep Submicron Metal-Oxide-Semiconductor Field Effect Transistors

A simple, flexible inverse modeling technique for deep submicron metal-oxide-semiconductor field effect transistors (MOSFETs), which is based on capacitance versus voltage (C–V ) and current versus voltage (I–V ) data measured in the so-called linear device operation regime is presented. Based on the resultant device structure and doping profile, device simulation yields good results not only for the linear regime but also under hot-carrier conditions. Substrate current, for example, is well reproduced over more than five orders of magnitude. Since the polysilicon-gate doping profile, the channel doping profile and the source/drain doping profile are extracted separately, they can be varied independently, and it is possible to predict the impact of process parameter variation. Good agreement between the simulation and measurement results is found for devices with different channel implants, shallow source/drain-extension implants or oxide thicknesses without any further inverse modeling.

Accurate prediction of hot-carrier effects for a deep sub-/spl mu/m CMOS technology based on inverse modeling and full band Monte Carlo device simulation

The ultimate goal of device modeling is the accurate prediction of device characteristics before the technological realisation. Due to insufficiencies of process simulation and to a lesser extent of device simulation this goal has not yet been reached. The aim of this work is to reduce the number of wafers in split lots used to investigate the effects of device parameter variation by predicting these effects with device modeling. Our approach is based on a device model (geometry and doping profile) which is extracted for one wafer by inverse modeling. This model is then used to predict the effects of parameter variation by device simulation with Galene III and our full band Monte Carlo (FB-MC) program Falcon. In this work we apply the new method to a state of the art 0.25/spl mu/m-CMOS technology and validate the approach by comparison with experiment.

Fully considered layout variation analysis and compact modeling of MOSFETs and its application to circuit simulation

We have developed a total system of circuit design to treat dependency of MOSFET electric characteristics on layout patterns. Our new methodology with two-step multivariate analysis realizes highly reliable compact modeling, and its application to SPICE simulation significantly improves accuracy of circuit modeling. Our system is a powerful tool of design for manufacturing in 65 nm technology node and beyond.

Test structures and measurement of gate sidewall junction capacitance in MOSFETs

A simple method of measuring the gate sidewall capacitance (c/sub jg/) in MOSFETs is presented. C/sub jg/ measurement of a short-channel transistor (Lmin = 40 nm) was successfully achieved by 2-port S-parameter measurement. Furthermore, a merging of source and drain depletion layers and an increase in substrate resistance, both caused by expansion of source and drain depletion layers, were observed through C/sub jg/ measurement for the first time.

Inverse modeling-a promising approach to know what is made and what should be made

Inverse modeling is a promising approach to know device structures made in experiments. We show our inverse modeling approach and its efficiency by demonstrating accurate extraction of deep submicron MOSFET structures. We also show that our approach can predict device performance to optimize its structure for required specification.

Parasitic resistance analysis for deep submicron CMOS with inverse modeling

Reducing parasitic series resistance is an important issue for producing deep-submicron high-speed CMOS. Some valuable methods for determining parasitic resistance have been developed. However the extracted parasitic resistance for the pMOS (1000 (Omega) (mu) m) is much larger than rough estimation base of extension sheet resistance, silicide-bulk contact resistance and silicide sheet resistance would indicate. This paper described the inverse modeling technique to determine the active doping profile from measured CV and IV characteristics. We found that contribution of extension profile to the parasitic resistance was about 80% and the rest was caused by silicide-bulk contact resistance. The reason is that only 5% of implanted boron was activated. For more complete activation, a higher RTA temperature is effective. RTA at a temperature of 1050 degrees Celsius for 5 seconds confirmed by spreading resistance measurements that the activation ratio was three times larger than that at a temperature of 1000 degrees Celsius for 10 seconds. Consequently a parasitic resistance reduction of 100 (Omega) can be expected by using the higher temperature process.