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Publication
Featured researches published by Seiji Ishihara.
electronic components and technology conference | 2002
Yuji Yano; Takuya Sugiyama; Seiji Ishihara; Yasuki Fukui; Hiroyuki Juso; Koji Miyata; Yoshiki Sota; Kazuya Fujita
In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.
electronic components and technology conference | 2003
Takuya Sugiyama; Yuji Yano; Seiji Ishihara; T. Maruyama; Hiroyuki Juso; T. Kirnura; M. Kada
With the development of mobile applications, there has been constant growth in system scale integration, and there is a need for improved mounting density to achieve further miniaturization. In order to meet these needs, we have developed a system in package (SIP), in which packages are stacked in three dimensions using an existing process.’’ By using this type of package, it is possible to realize highcapacity memory, and combination packages incorporating memory as well as logic LSI modules such as ASICs. We evaluated the reliability of three-dimensional SIPs with the aim of makimg them practical. We focused on evaluating reliability in response to thermal or mechanical stress after mounting. First we evaluated memory-stacked SIPs, and as a result found that reliability in the area of thermal stress is affected by the orientation of the chip’s operating surface, and the presence of dummy balls. Reliability also declines as the number of package stacking layers increases, but we improved reliability by changing the land stmcture to the non solder mask defmed (NSMD) type. For mechanical stress testing, we achieved a level that presents no problems for practical use by using underfill
Archive | 2001
Hiroyuki Juso; Yasuki Fukui; Yuji Yano; Seiji Ishihara
Archive | 2006
Yuji Yano; Seiji Ishihara
Archive | 2005
Seiji Ishihara; Yuji Yano; 祐司 矢野; 誠治 石原
Archive | 2003
Seiji Ishihara; 誠治 石原
Archive | 2000
Yasuki Fukui; Seiji Ishihara; Hiroyuki Juso; Yuji Yano; 博行 十楚; 祐司 矢野; 誠治 石原; 靖樹 福井
Archive | 2007
Seiji Ishihara; 誠治 石原
Archive | 1997
Seiji Ishihara; Koji Miyata; Takuya Sugiyama; Kazuo Tamaoki; 浩司 宮田; 拓也 杉山; 和雄 玉置; 誠治 石原
Archive | 2010
Seiji Ishihara; Hiroyuki Nakanishi; Kiyoji Shimano; Masato Yokobayashi; 宏之 中西; 喜代治 島野; 政人 横林; 誠治 石原