Yoshiki Sota

Three-dimensional very thin stacked packaging technology for SiP

In order to achieve the greater compactness, lightness, high- and multi-functionality required of mobile equipment and other electronic devices, we have developed 3D packaging technology which enables free stacking, at the package level, of ultra-thin CSP (which contain 2 or 1 LSI chip(s)). By stacking at the package level, there are no yield problems, and it is easy to perform independent electrical testing, so it is possible to achieve multi-level stacking while freely combining different kinds of LSI chips like memory or ASIC. By making chips and resin molding thinner, lowering wire loops and optimizing the package structure, we achieved higher package density: a single unit (2 chips) package height of 0.55 mmMax., 2 layers (4 chips) with a unit package height of 1.0 mmMax., and 3 layers (6 chips) with a unit package height of 1.5 mmMax. This technology makes it possible to offer ultra-compact systems-in-package (logic + memory) and high-capacity composite memories.

Triple-chip stacked CSP

As electronic devices, particularly cellular telephones, become more compact, lighter in weight and more functional, it is becoming necessary to decrease the number of components mounted on the substrate, decrease their mounting area, and decrease their weight. To meet this need, in April of 1998 Sharp successfully developed the stacked CSP, an ultra-compact package housing two LSIs laid one on top of the other. Now mass-produced as a combination memory device containing both flash memory and SRAM for use in cellular telephones, the stacked CSP has become the most used memory package for cellular telephones. As information services provided through cellular telephones continue to grow, the LSI system can be expected to become larger in scale and the memory devices required to have greater capacity. These will in turn require packages with even higher mounting densities. To satisfy this need, Sharp developed the Triple-Chip Stacked CSP housing three LSIs. Mass production began in August 1999.

Development of highly reliable CSP

High density packages are demanded due to recent miniaturization for personal tools. In order to satisfy these demands, development is being done in various companies in CSP (Chip-Size-Package or Chip-Scale-Package) in which its package size in nearly the same as LSI chip and function is close to bare chip. We have developed and mass production of CSP using current equipment based on a proven packaging technology involving wire bonding and transfer mold technology. We can realize 0.8 mm terminal pitch and from the memory with a few to ASIC with 300 in pin counts using this technology and correspond to various matrix layout independent of LSI chip size. The CSP developed by us uses polyimide with one side pattern. After mounting the LSI chip and connecting with wire bonding, one side is contained with mold resin. External terminals use solder ball which is of area array structure. In order to minimize the outline size of the package to be as close to the LSI chip as possible, various technologies were developed such as ultra-short loop wire bonding technology of a half length compared to conventional loop length, super-small solder ball mounting technology how far size of 0.3 mm /spl phi/, low stress high precision cutting technology with laser and fine pattern technology of substrate. Furthermore, in order to maintain high reliability to the level attained in conventional plastic packages, development was done on thermally resistant insulator and on mold resin which increase the adherence with substrate. Work was also done to reduce the effect of moisture in package through vent hole in pattern substrate. Regarding mounting to the PCB, the CSP developed by us is able to be mounted by merely recognizing of packages high precision outline with laser cutting technology and mounting with other packages is possible due to collective reflow which utilize conventional technologies. Reliability evaluation after mounting has shown that it is very realistic levels for us. By developing the above technologies and developing new materials, packaging technology for a highly reliable CSP was made possible.

Development of high density memory IC package by stacking IC chips

A stacked chip package in which two memory chips are stacked with no increase in package thickness has been developed. The majority of its material composition is nearly identical to that used for conventional TSOP packages. Chips are mounted on the top and bottom sides of a die pad. This arrangement keeps the assembly process from becoming too complex and allows full use of existing manufacturing facilities. Cracking of the passivation was avoided by coating the chip surface with a polyimide film and using a buffer on the jig. Package quality was maintained even if the jig buffer contacted the chip surface with a polyimide during the die and wire bonding processes. The overall package reliability is equivalent to that of conventional TSOPs.