Seishi Notomi

A 1.2-ns HEMT 64-kb SRAM

A 1.2-ns emitter-coupled-logic (ECL)-compatible 64-kb static RAM using 0.60- mu m gate high-electron-mobility-transistor (HEMT) technology was developed. To achieve fast access time, the memory cell array was divided into sixteen 4-kb memory planes and a data-line equalization technique was adopted. The chip power consumption was suppressed to 5.9 W by using three power supply voltages (-1.0, -2.0, and -3.6 V) and a normally off (E/D) source-follower buffer for the word driver circuit. A new device fabrication technique, the HEMT double-etch-stop process, enabled the RAM to be fabricated in simple and fewer processing steps and reduced the chip dimensions to 7.4*6.5 mm. >

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay. >

A subnanosecond HEMT 1Kb SRAM

HIGH-SPEED LSIs have been required for high performance mainframe computers. The development of High Electron Mobility Transistor (HEMT)’ is felt to be applicable for high-speed logic operations. This paper will report on the design of a I K x l b fully static RAM using HEMT. The RAM was constructed with Enhancement/Depletion (E/D) type DCFL circuitry, using 1 . 5 ~ gate devices, and 3pm line process. The memory cell size measures 55 x 3 9 p , and the chip size is 3.0 x 2.9mm. Address access time of 0.911s and an operating power of 360mW at liquid nitrogen temperature have been obtained. A photomicrograph of the RAM is shown in Figure 1. The RAM is organized into 1024 word x lb , and arranged as a 32 x 32 matrix. Using a depletion type HEMT for load devices, E/D type DCFL circuits were employed as the basic circuit. The memory cell is a 6-transistor cross-coupled flipflop circuit with switching devices having gate lengths of 2.Opm. For peripheral circuits, 1 . 5 p gate switching device was chosen for performance reasons, and long gate devices were used as load devices. The circuit diagram of the RAM is shown in Figure 2. To obtain a high-speed operation, sufficiently large operating current was assigned to peripheral circuits, especially to the address buffer, word driver, and output buffer which have large wiring capacitances. As a result, the entire peripheral circuit which has 15% of the total device count, dissipates 85% of the chip dissipation power. As seen in Figure 1, the total area of the peripheral circuits is same as the cell array. But no particular power-down technique was employed in this design. A differential amplifier type sensing circuit and a bit line pull-up scheme were adopted to fetch data in short time from the low power memory cell. To drive large off-chip capacitance quickly, a four-stage output buffer amplifier was used with a final stage of a push-pull type output circuit constructed of high-current enhancement type devices. To obtain

Ultrahigh speed high electron mobility transistor large scale integration technology

Current status and recent advances in high electron mobility transistor (HEMT) technology for high performance very large scale integration (VLSI) are presented with the focus on material, self‐alignment device fabrication, and HEMT large‐scale integration (LSI) implementations. HEMT is a very promising device for ultrahigh speed LSI/VLSI due to the supermobility GaAs/AlGaAs heterojunction structure. The technological challenges for large scale integrations are discussed with refined HEMT with self‐aligned gate structure, controllability of device parameters, and molecular beam epitaxy material problems. Master–slave flip–flop, divide‐by‐two circuits achieved the internal logic delay of 22 ps per gate at 77 K at a fan‐out of about 2, roughly three times faster than that of GaAs metal‐semiconductor field‐effect transistor technology. HEMT has already made it possible to develop 16 kb static random access memory (RAM) and a 1.5‐kgate gate array, demonstrating high speed LSI operations. With submicron gates,...

A subnanosecond HEMT 1-kbit static RAM

The RAM has a memory capacity of 1024 bits and integrates 7244 high-electron-mobility transistor (HEMT) devices into 1024-words/spl times/1-bit organization. The RAM uses enhancement/depletion-type direct-coupled FET logic (DCFL) circuitry as a basic circuit and can operate fully statically. The design rules used are a 1.5-/spl mu/m minimum gate length, a 2/spl times/2-/spl mu/m/SUP 2/ contact hole, and a 3-/spl mu/m linewidth and spacing of the wiring electrodes. The memory cell is 55/spl times/39 /spl mu/m and the chip is 3.0/spl times/2.9 mm. The RAM is fabricated on an AlGaAs/GaAs heterojunction epi-structure grown by molecular beam epitaxy on a Cr-doped 2-in LEC GaAs substrate wafer. A subnanosecond access time of 0.87 ns with a 1.60-V supply and 360-mW dissipation has been attained at liquid nitrogen temperature.