Masahisa Suzuki

Pseudomorphic n-InGaP/InGaAs/GaAs grown by MOVPE for HEMT LSIs

InGaP/InGaAs/GaAs heterostructures were grown by atmospheric pressure MOVPE. Excellent uniformity was obtained for doping concentration, thickness, and composition of the epitaxial layers by rotating the substrate and cooling the inner tube. The optimum gas switching sequence for achieving sufficient mobility and sheet carrier concentration was found. Enhancement-mode and depletion-mode HEMTs were fabricated using the very thin InGaP layer as an etching stopper layer. These are essential for the fabrication of HEMT LSI circuits. The discrete devices do not exhibit I–V collapse at low temperature. Short channel effects are negligible for gate lengths as small as 0.15 μm, owing to good carrier confinement in the pseudomorphic quantum well channel and a high aspect ratio under the thin n-InGaP layer. These advantages make InGaP/InGaAs/GaAs heterostructures well suited to HEMT LSIs applications.

Recent advances in ultrahigh-speed HEMT LSI technology

The current status of, and recent advances in, high electron mobility transistor (HEMT) technology for high-performance submicrometer VLSI are presented with a focus on materials, self-aligned device fabrication, and HEMT LSI implementation. The HEMT is a very promising device for ultrahigh-speed LSI/VLSI applications because of the high-mobility GaAs/AlGaAs heterojunction structure. The authors project an optimized chip delay of 40 ps at 10 K-gate VLSI at room temperature. >

A 40-ps high electron mobility transistor 4.1 K gate array

A high-electron mobility transistor (HEMT) 4.1 K-gate array has been developed, using a selective dry etching process and a MBE (molecular-beam epitaxy) growth technology. The circuit design uses direct-coupled FET logic (DCFL). The chip contains 4096 NOR gates, each with a 0.8- mu m gate length, and measures 6.3 mm*4.8 mm. A basic gate delay of 40 ps has been achieved. A 16*16-bit parallel multiplier, used to test this array, has a multiplication time of 4.1 ns at 300 K, where the power dissipation is 6.2 W. >

A 1.2-ns HEMT 64-kb SRAM

A 1.2-ns emitter-coupled-logic (ECL)-compatible 64-kb static RAM using 0.60- mu m gate high-electron-mobility-transistor (HEMT) technology was developed. To achieve fast access time, the memory cell array was divided into sixteen 4-kb memory planes and a data-line equalization technique was adopted. The chip power consumption was suppressed to 5.9 W by using three power supply voltages (-1.0, -2.0, and -3.6 V) and a normally off (E/D) source-follower buffer for the word driver circuit. A new device fabrication technique, the HEMT double-etch-stop process, enabled the RAM to be fabricated in simple and fewer processing steps and reduced the chip dimensions to 7.4*6.5 mm. >

Reduction of backgating effect in MBE-Grown GaAs/AlGaAs HEMT's

We have investigated the backgating effect in high electron mobility transistors (HEMTs) fabricated on MBE-grown GaAs/AlGaAs layers, which is undesirable for LSI fabrication. Comparing five different types of devices, we related the backgating effect to the interface between the GaAs substrate and the undoped GaAs buffer layer. By using a thermally etched GaAs substrate, we successfully reduced the backgating to the same order as that of ion-implanted GaAs MESFETs.

Uniform and abrupt InGaP/GaAs selectively doped heterostructures grown by MOVPE for HEMT ICs

Abstract Uniform and abrupt Si-doped InGaP/GaAs selectively doped heterostructures are grown by atmospheric-pressure metalorganic chemical vapor deposition, and the feasibility of the material system for HEMT ICs is demonstrated for the first time. The uniformities of donor concentration and thickness of Si-doped InGaP layers are ±4.5% and ±1.5%. These values are small enough for IC applications. The mobility at 4.2 K and the two-dimensional electron gas concentration obtained from Shubnikov-De Haas oscillation measurements are 89,300 cm2/V·s and 8.9×1011 cm−2 for samples with a spacer thickness of 5.5 nm. HEMT IC structures were grown to evaluate the device characteristics. It was shown that enhancement- and depletio-mode HEMTs can be fabricated on the same wafer by selective etching technique. The characteristics of the transistors exhibit no instability at 77 K.

Recent progress in MOVPE for HEMT LSIs

An MOVPE technique capable of mass-producing selectively doped AlGaAs/GaAs heterostructure has been developed for HEMT LSI applications. A barrel-type reactor developed has a load capacity of twelve 3-inch wafers. Wafer rotation resulted in extremely uniform epitaxial layers. The variations in both layer thickness and carrier concentration of a Si-doped AlGaAs layer are less than ±1% across a 3-inch wafer. The wafer-to-wafer variations among the twelve wafers are ±1.1% for layer thickness and ±1.8% for carrier concentration. The reactor routinely produces high-quality AlGaAs/GaAs selectively doped heterostructures. A mobility of 121,000 cm2/V ·s with a sheet carrier concentration of 6.46×1011 cm-2 was obtained at77 K for the heterostructure having a 7-nm spacer layer. The total particle density on an epitaxial layer was reduced to less than 10 cm-2. The fabricated HEMTs showed excellent uniformity of the threshold voltage. The standard deviations were as small as 10.1 mV for E-HEMTs and 16.1 mV for D-HEMTs over an entire 3-inch wafer.

A 45 K-gate HEMT array with 35-ps DCFL and 50-ps BDCFL gates

A 45 K-gate emitter-coupled-logic (ECL)-compatible array with unbuffered and buffered direct-coupled FET-logic (DCFL and BDCFL) gates has been developed using 0.6- mu m-gate high-electron-mobility transistors (HEMTs) and four-level gold-based interconnects. The high-speed DCFL gates and more functional BDCFL gates are used to replace ECL macros efficiently. The basic cell, equivalent to four three-input NOR gates, consists of 12 enhancement-mode (E-mode) HEMTs, four depletion mode (D-mode) HEMTs, and two source-follower buffers. The basic gate delay times are 35 ps for 0.24-mW unbuffered DCFL gates and 50 ps for 0.38-mW BDCFL gates. The gate array chip is 9.8*9.8 mm and contains 45600 gates. The chip dissipates 11 W in 80% gate use. Silylated polymethyl silsequioxane (PMSS), which has a low dielectric constant of 3, is used for the interlayer dielectrics to reduce wiring delay. >

A gigahertz cryogenic HEMT pseudorandom number generator chip set

A 1-GHz high electron mobility transistor (HEMT) chip set for a cryogenic pseudorandom number generator subsystem that has enhancement/depletion (ED) direct-coupled FET logic (DCFL) circuits and operates at liquid nitrogen temperature is described. Using HEMT circuitry at cryogenic temperatures has several advantages. The DC characteristics of the HEMT are improved. The resistance of interconnecting metal at 77 K is about one-third that at room temperature. This minimizes interconnection delay, which is defined by the RC time constant, and simplifies the layout of power and ground lines. Heat is removed from the IC by immersing the bare chip in liquid nitrogen. A 32-b pseudorandom number generator for an external unit of a scientific computing system demonstrates the feasibility of the HEMT-IC-based computer operating at 77 K.<<ETX>>

Se-doped AlGaAs/GaAs HEMTs for stable low-temperature operation

The fabrication of Se-doped AlGaAs/GaAs high electron mobility transistors (HEMTs) is discussed. Because the DX center concentration in Se-doped AlGaAs layers is lower than in Si-doped layers, the drain-current collapses much less at 77 K. The Se-doped HEMTs are therefore suitable for application in low-temperature LSI.<<ETX>>