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Dive into the research topics where Sejal N. Chheda is active.

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Featured researches published by Sejal N. Chheda.


international electron devices meeting | 1999

A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films

Tat-Kwan Yu; Sejal N. Chheda; J. Ko; Mark S. Roberton; Aykut Dengi; Edward O. Travis

This paper presents a new two-dimensional (2-D) low pass filter model for the prediction of post-chemical-mechanical polishing (CMP) die level wafer topography variation caused by the interconnect metal density of a circuit layout. It is demonstrated that the local smoothing and planarization effects of an ILD polishing process can be characterized accurately (in the frequency domain) by a polynomial equation with a small number of fitted parameters. In this method, the design specific metal density patterns with millions of shapes are first captured in the frequency domain using a 2-D Fast Fourier Transform (FFT). A fitted low pass filter CMP model is then applied to filter/remove short range pattern variation. (Die level topography variations are not removed by CMP effectively). Finally, the post-CMP smoothed topography in the spatial domain is computed from inverse FFT. Model predictions and experimental data are compared in three examples (a) a test structure, (b) a die with shallow trench isolation (c) cumulative topography of a die after ILD1, 1LD2 and ILD3 polishing.


21st Annual BACUS Symposium on Photomask Technology | 2002

Model-based OPC methodology for 0.13 micron technology

Vishnu G. Kamat; Kent G. Green; Sejal N. Chheda; Sven Muehle; Venkat Kolagunta; Bill Wilkinson; Cecilia E. Philbin

As we move towards smaller dimensions and denser circuits, Model Based OPC has become a critical and indispensable tool to achieve feature fidelity for random logic and very small bitcell patterns. Model-Based OPC s used to overcome the effects due to the reticle manufacturing process and the photolithography process which are essentially low pass filters, with the objective of returning the intended drawn feature on wafer within acceptable error. In this paper we demonstrate its capabilities and flexibility with the development of a mixed Model-based/Rule based OPC approach that covers all categories of features for the active layer and the heuristics that justify this approach. We discuss along with experimental results the parameterized variations that are possible with Model Based OPC (MBOPC)and the optimization required as a result within the paradigm of a 248nm-lithography process for the 0.13-micron technology. Data and manufacturability issues are discussed that are an important consideration for a feasible MBOPC solution.


Archive | 1999

Semiconductor device and a process for designing a mask

Edward O. Travis; Aykut Dengi; Sejal N. Chheda; Tat-Kwan Yu; Mark S. Roberton; Ruiqi Tian


Archive | 2001

Method of forming an integrated circuit device using dummy features and structure thereof

Edward O. Travis; Sejal N. Chheda; Ruiqi Tian


Archive | 2001

Method for adding features to a design layout and process for designing a mask

Edward O. Travis; Aykut Dengi; Sejal N. Chheda; Tat-Kwan Yu; Mark S. Roberton; Ruiqi Tian; Robert Boone; Alfred J. Reich


Archive | 2001

Semiconductor tiling structure and method of formation

Sejal N. Chheda; Edward O. Travis


Archive | 1999

Semiconductor device, a process for a semiconductor device, and a process for making a masking database

Edward O. Travis; Sejal N. Chheda; Bradley P. Smith; Ruiqi Tian


Archive | 2000

PROCESS FOR DESIGNING A MASK

Edward O. Travis; Aykut Dengi; Sejal N. Chheda; Tat-Kwan Yu; Mark S. Roberton; Ruiqi Tian


Archive | 2000

Selective sizing of features to compensate for resist thickness variations in semiconductor devices

Bradley P. Smith; Edward O. Travis; Sejal N. Chheda; Ruiqi Tian


Archive | 2003

SEMICONDUCTOR DEVICE AND PROCESS THEREFOR

Edward O. Travis; Sejal N. Chheda; Bradley P. Smith; Tian Ruiqi

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