Tat-Kwan Yu

A statistical polishing pad model for chemical-mechanical polishing

Chemical mechanical polishing (CMP) has emerged as a critical technology for advanced integrated circuit fabrication. This paper presents for the first time a physical CMP model that includes the effects of polishing pad roughness and dynamic interaction between pad and wafer. Two new feature-scale polishing mechanisms based on asperity theory are proposed and investigated experimentally. a statistical asperity model is first introduced and applied to characterize surface roughness of polishing pads. The data is then used to calculate pad-wafer contact properties and predict feature-scale polishing rates. CMP experiments suggest that the time-dependent deformation of polishing pads and asperity-device interaction both affect planarization of device features.<<ETX>>

Realistic electromigration lifetime projection of VLSI interconnects

Abstract Tungsten plug contacts/vias electromigration experiments have been performed using a variety of test structures under different stress conditions. It was found that electromigration failures, failure mechanisms of tungsten plug contacts/vias, were strongly influenced by the test structures and stress conditions. This paper discusses the effect of test structures and stress conditions on electromigration failure for realistic lifetime projection of VLSI interconnects.

Combined asperity contact and fluid flow model for chemical-mechanical polishing

This paper presents, for the first time, a physical model of chemical-mechanical polishing (CMP) that combine the effects of polishing pad roughness and slurry hydrodynamic pressure. Recently, the authors introduced a statistical asperity model to analyze contact of wafer and the polishing pad. This model is extended to include slurry flow hydrodynamics. Fluid film thickness between the wafer and pad is first estimated from measured pad roughness. Fluid pressure is then calculated from finite element simulation. The model is used to investigate parametric effects of pressure, platen velocity and pad roughness.<<ETX>>

A two-dimensional low pass filter model for die-level topography variation resulting from chemical mechanical polishing of ILD films

This paper presents a new two-dimensional (2-D) low pass filter model for the prediction of post-chemical-mechanical polishing (CMP) die level wafer topography variation caused by the interconnect metal density of a circuit layout. It is demonstrated that the local smoothing and planarization effects of an ILD polishing process can be characterized accurately (in the frequency domain) by a polynomial equation with a small number of fitted parameters. In this method, the design specific metal density patterns with millions of shapes are first captured in the frequency domain using a 2-D Fast Fourier Transform (FFT). A fitted low pass filter CMP model is then applied to filter/remove short range pattern variation. (Die level topography variations are not removed by CMP effectively). Finally, the post-CMP smoothed topography in the spatial domain is computed from inverse FFT. Model predictions and experimental data are compared in three examples (a) a test structure, (b) a die with shallow trench isolation (c) cumulative topography of a die after ILD1, 1LD2 and ILD3 polishing.

An EEPROM model for low power circuit design and simulation

A CAD EEPROM circuit model is essential to the design/optimization of low power non-volatile memory products. This paper presents a new FETMOS EEPROM circuit model that includes both Fowler-Nordheim and band-to-band tunneling. A DC model for FETMOS operation is derived and then extended to transient device operation. The model has been implemented into SPICE and applied to simulate the program/erase of a FETMOS bitcell and threshold voltage shifts under various bias conditions.<<ETX>>

Combined reactor, wafer, and feature scale simulation of selective silicon epitaxial growth

A combined approach to the modeling of selective epitaxial silicon growth (SEG) is presented. The simulations consider the following effects: reactor fluid dynamics, gas chemistry, mass transport in the stagnant layer, and device profile evolution. Reactor-scale, wafer-scale and feature-scale simulations are used to model these mechanisms which have a wide range of physical dimensions. Experiments to identify the effects of HCl on silicon growth rates have been performed. The experimental results show that the main effect of HCl is modulation of reactant gas composition, and they provide the rate constants necessary to simulate local loading effects in the stagnant layer simulation.<<ETX>>