Seo-Woo Nam

High performance PRAM cell scalable to sub-20nm technology with below 4F2 cell size, extendable to DRAM applications

A PRAM cell with great scalability and high speed operation capability with excellent reliability below 20nm technology was demonstrated. This has the meaning of the potential applicable to the technology area of scaling limitation of DRAM cell. We fabricated a confined PRAM cell with 7.5nm×17nm of below 4F2. In particular, Sb-rich Ge-Sb-Te phase change material was employed for high speed operation below 30nsec. The excellent writing endurance performance was predicted to maintain up to 6.5E15cycles by reset program energy acceleration. Its data retention was 4.5 years at 85°C which is enough for DRAM application.

Si FinFET based 10nm technology with multi Vt gate stack for low power and high performance applications

10nm logic technology using Si FinFET is developed for low power and high performance applications. Power-speed gain of 27% compared to 14nm technology node was obtained using four key developments: 1) advanced gate stack engineering enabling 4 multi-Vt devices, 2) 3rd generation Fin technology, 3) highly doped source/drain (S/D), and 4) contact resistance optimization. CVD liner for BEOL process was also applied for better metal fill capability. Finally yield of the smallest ever SRAM with 0.04um2 SRAM bit-cell size was demonstrated.

Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell

Scalability of interface driven perpendicular magnetic anisotropy (i-PMA) magnetic tunnel junctions (MTJs) has been improved down to 1X node which verifies STT-MRAM for future standalone memory. With developing a novel damage-less MTJ patterning process, robust magnetic and electrical performances of i-PMA MTJ cell down to 15 nm node could be achieved.

Electromigration Failure Mechanism and Lifetime Expectation for Bi-Modal Distribution in Cu/Low-k Interconnect

The root cause and an approach to lifetime expectation of bi-modal distribution in Cu/low-k interconnect have been elucidated through experimental and simulation results. The early mode with short failure time and voids at via bottom interface, could be explained by pre-existing voids and large current density resulting from gouging via bottom profile. A high compressive SiCN making Cu/SiCN interface near via into tensile stress causes void nucleation in its specified sites, which indicate the late mode. And component lifetime can be predicted using the data obtained only from early failure, because of the same in activation energy and acceleration factor. This comprehension for bi-modal behavior is helpful in EM reliability of technology node beyond 45 nm.

Highly manufacturable 7nm FinFET technology featuring EUV lithography for low power and high performance applications

7nm CMOS FinFET technology featuring EUV lithography, 4th gen. dual Fin and 2nd gen. multi-eWF gate stack is presented, providing 20% faster speed or consuming 35% less total power over 10nm technology [1]. EUV lithography, fully applied to MOL contacts and minimum-pitched metal/via interconnects, can reduce >25% mask steps with higher fidelity and smaller CD variation. AVT of 6T HD SRAM cell are 1.29 for PD (PG) and 1.34 for PU, respectively.

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O3-TEOS films show more tensile stress value about twice than that of an as-deposited O3 -TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation

Highly manufacturable Cu/low-k dual damascene process integration for 65nm technology node

A manufacturable Cu/low-k multilevel interconnects have been integrated using HSQ-via-fill dual damascene process for 65nm node as stated in K.-W. Lee et al. (2003). By introducing non-porous type SiOC film (k=2.7) without trench etch stopper and capping oxide, we obtained the effective k (keff) less than 3.0 for 65nm design rule. Simple and reliable process was achieved by improved unit process technologies such as damage-free capping oxide, abrasive free low-k direct polishing, advanced ionized PVD (AiPVD) barrier metal and bi-layer dielectric barriers, etc. according to K.C. Park et al. (2003).

Improvement of reliability and speed of phase change memory devices with N7.9(Ge46.9Bi7.2Te45.9) films

In this study, we propose a nitrogen-incorporated GeBiTe ternary phase of N7.9(Ge46.9Bi7.2Te45.9) as a phase change material for reliable PCM (Phase Change Memory) with high speed operation. We found that the N7.9(Ge46.9Bi7.2Te45.9) film shows the resistance value of 40 kΩ after annealing at 440oC for 10 minutes, which is much higher than the value of 3.4 kΩ in the case of conventional N7.0(Ge22.0Sb22.0Te56.0) films. A set operation time of 14 nsec was achieved in the devices due to the increased probability of the nucleation by the addition of the elemental Bi. The long data retention time of 10 years at 85oC on the base of 1% failure was obtained as the result of higher activation energy of 2.52 eV for the crystallization compared to the case of N7.0(Ge22.0Sb22.0Te56.0) film, in which the activation energy is 2.1 eV. In addition, a reset current reduction of 27% and longer cycles of endurance as much as 2 order of magnitude compared to the case of N7.0(Ge22.0Sb22.0Te56.0) were observed at a set operatio...