Hong-jae Shin

Low Dielectric Constant 3MS α-SiC:H as Cu Diffusion Barrier Layer in Cu Dual Damascene Process

The primary candidate for the barrier/etch stop layer in damascene process is silicon nitride. However, silicon nitride has a high dielectric constant. To reduce the effective dielectric constant in the copper damascene structure, silicon carbide, which is prepared by plasma enhanced chemical vapor deposition (PECVD) using 3 methyl silane source (Z3MS), is studied for the dielectric copper diffusion barrier. The dielectric constant of PECVD α-SiC:H is varied from 4.0 to 7.0 and the fourier transform infrared (FTIR) spectra peak intensity ratio of Si–CH3 bond to Si–C is also examined. The reduction in dielectric constant of α-SiC:H using 3MS gas seems to be related to the decreased density upon incorporation of Si–CH3 groups. The value of capacitance with α-SiC is 8–10% lower than that with PECVD SiN. The leakage current with α-SiC:H barrier is lower by 1 order of magnitude than that with PECVD SiN barrier.

New insight into stress induced voiding mechanism in Cu interconnects

An effective method was used for the failure analysis of stress induced voids. Instead of conventional vertical inspection, the lower wide copper surface connected to the via was investigated after removing the passivation layer and upper copper layer. Many voids were observed at the grain boundary area, regardless of via location. According to the step by step inspection of that surface, many small voids were generated at the grain boundary area after dielectric barrier deposition, even before an HTS (high temperature storage) test, and some of the voids were grown after HTS, preferentially at the grain boundary corners. This result implies that unlucky landing of via over the grain boundary area would be the main cause of stress induced void under the via.

Integration and reliability of a noble TiZr/TiZrN alloy barrier for Cu/low-k interconnects

We have investigated TiZr alloy as a new Cu barrier material for low cost and high performance Cu/low-k interconnects. TiZrN ternary nitride was used as a Cu diffusion barrier and TiZr as an adhesion promotion layer. The issue of metal line resistance shift was suppressed using a novel 2-step annealing procedure. Multi-level Cu metal wiring integration was successfully carried out and the enhanced electrical performance of low via resistance with high via yield was obtained. Improved electromigration and stress-induced voiding resistances also have been demonstrated.

Pre-Metal Dielectric Stress Engineering by a Novel Plasma Treatment and Integration Scheme for nMOS Performance Improvement

For the first time, a transistor performance improvement is achieved by increasing the tensile stress of O3-TEOS pre-metal dielectric (PMD) using a novel plasma treatment and integration scheme. Plasma-treated O3-TEOS films show more tensile stress value about twice than that of an as-deposited O3 -TEOS film. The novel process shows up to 10% improvement of Ion for nMOS without any cost of pMOS degradation