Seog-Heon Ham

A 2.1Mpixel 120frame/s CMOS image sensor with column-parallel ΔΣ ADC architecture

Over the last few years, the demands for high-density and high-speed imaging have increased drastically. Since CMOS image sensors have the advantages of low power consumption and easy system integration, they have become dominant over CCDs in the consumer market [1–4]. A column-parallel ADC architecture is the most widely used ADC in CMOS image sensors for high-speed and low-power operation [2–6]. The column-parallel architecture can be classified as: successive-approximation register (SAR) [2], cyclic [3], single-slope (SS) [4], and delta-sigma (ΔΣ) [5,6] ADCs. Although SAR ADCs have been utilized for high-speed imaging, such as UDTV, they require a DAC in a column, whose area is unacceptably large for consumer electronics with a fine pixel pitch. Cyclic ADCs have also been reported in high-speed imaging, but they have high power consumption and high noise levels. Since SS ADCs provide relatively high resolution with minimum area, they have been widely used in CMOS image sensors. However, SS ADCs require very fast clock signals leading to high power consumption in the case of high-speed imaging. Although ΔΣ ADCs have been investigated for low-noise imaging, they have only been applied for low-speed imaging with large pixel pitch because of the complexity of ΔΣ modulators and following decimation filters.

A 1.1e- temporal noise 1/3.2-inch 8Mpixel CMOS image sensor using pseudo-multiple sampling

The noise performance of CMOS image sensors has improved significantly. The most popular way to reduce readout circuit noise is amplifying pixel output using a preamplifier at the foremost stage of readout chain to suppress the noise of following readout chains in high analog gain [1–3]. Another approach is multiple sampling which can reduce temporal noise of pixel and readout circuit by sampling the same pixel repeatedly and processing (generally averaging) the sampled data [4, 5]. However, both approaches require additional circuitry in the column readout chain which requires extra silicon area and power consumption. Furthermore, it is hard to implement a decent per-column amplifier in a small pixel pitch sensor, such as 1.4µm pixel, because of narrow layout space. In addition, the second approach requires longer readout time proportional to the number of samples. This paper presents a cost-effective low noise CMOS image sensor readout chain using pseudo-multiple sampling technique.

Effects of on-chip and off-chip decoupling capacitors on electromagnetic radiated emission

Recently, electromagnetic interference (EMI) and radiated emission has become a major problem for high-speed circuit and package designers, and it is likely to become even severe in the future. However, until recently, designers of integrated circuit and package did not give much consideration to electromagnetic radiated emission and interference in their designs. Decoupling capacitors have been mostly used to reduce the power/ground bounce of high-speed digital system and boards. However, there has not been a systematic study to understand the effects of on-chip and off-chip decoupling capacitors on the electromagnetic radiated emission. In this paper, we report the simulation and the measurement results regarding the radiated emission due to the power/ground bounce. And we discuss the effects of the on-chip and off-chip decoupling capacitors to the power/ground bounce and the electromagnetic radiated emission. This circuit is simulated using HSPICE. Test ICs and printed circuit boards were designed and fabricated. Using a transverse electromagnetic (TEM) cell, the radiated electric field of the device under test (DUT) is measured. Combined placement of the on-chip and off-chip decoupling capacitor achieves more than 10 dB suppression of the radiated emission on the whole spectrum region. The design rule of the optimum placement of the decoupling capacitor was obtained.

A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- μm 1P4M process with pixel pitch of 2.25 μm . The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are +0.59/-0.83 LSB and +2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are the solution for a high-resolution ADC having tolerance of analog component errors. Oversampling reduces input temporal noise as well as the quantization error of the ADC itself [1]. However, an I-ΔΣ ADC is also classified as a slow ADC because it requires exponential conversion time to get higher bit resolution. To reduce conversion time, there are two alternative methods: 1) higher-order modulation, and 2) two-step conversion such as an extended-counting technique [2]. In this paper, the extended-counting (EC) method is used since a high-order structure requires more complex hardware and greater power consumption [1,2]. For a general two-step ADC, coarse conversion restricts the total ADC resolution since it determines accuracy of the residue. However, an EC ADC overcomes the accuracy limitation, since the I-ΔΣ can improve its precision through oversampling. Moreover, oversampling also suppresses the noise of the pixels source follower. Our 14b EC ADC is a blend of a 1st-order I-ΔΣ ADC and a cyclic ADC to simultaneously get high resolution and high speed.

Separated role of on-chip and on-PCB decoupling capacitors for reduction of radiated emission on printed circuit board

The power/ground fluctuation is known as a significant source of radiated emission. We discuss the separated functions of on-PCB and on-chip decoupling capacitors on the suppression of electromagnetic radiated emission. Due to the different ranges of parasitic inductance and the different locations of the on-chip current drivers, on-PCB and on-chip decoupling capacitors exhibit separated frequency characteristics in terms of suppression efficiency of radiation. The roles of on-PCB and on-chip decoupling capacitors are estimated by circuit simulation and a simple antenna model, and are confirmed by experiments. It is found that the on-chip decoupling capacitors are mainly effective for the suppression of radiated emission over 100 MHz frequency. Increase of the on-chip decoupling capacitance and decrease of the parasitic inductance of the package produce an improved suppression ratio at high frequency range. Combined placement and sizing of the decoupling capacitors have achieved more than 10 dB suppression of the electromagnetic radiated emission over a wide spectrum range.

CMOS image sensor with analog gamma correction using nonlinear single-slope ADC

A human eye has the logarithmic response over wide range of light intensity. Although the gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This paper proposes a CMOS image sensor (CIS) with nonlinear analog-to-digital converter (ADC) which performs analog gamma correction. The CIS with the proposed nonlinear ADC conversion scheme was fabricated with a 0.35-mum CMOS process. The test results show the improved image quality than digital gamma correction

Ramp Slope Built-in-Self-Calibration Scheme for Single-Slope Column Analog-to-Digital Converter Complementary Metal-Oxide-Semiconductor Image Sensor

The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal–oxide–semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-µm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.

0.37mW/Gb/s low power SLVS transmitter for battery powered applications

A power-efficient voltage-mode transmitter for battery powered mobile applications was designed. The proposed transmitter consists of a power optimized 16:2 serializer, a data-aligner, 2:1 multiplexing pre-driver, and an I/O driver with segment control for impedance matching. With scalable low-voltage signaling (SLVS) with the output swing of 200mVp-p and power optimization for digital blocks, 0.37mW/Gb/s power consumption was achieved. The test chip for 4.8 Gb/s interfaces was designed in a 65nm 1.2V supply CMOS logic process. The proposed I/O specifications are appropriate for MIPI M-PHY systems.

The electromagnetic radiation with phase difference in rectangular loop antenna or rectangular loop circuit

By using algebra, we showed that current phase difference should not be neglected when predicting the radiation of a loop antenna. The pattern of electric field is dependent on the position of the current source. The phase of electric field is dependent on the angle. In the rectangular loop antenna, either width or length is zero, but still there exists a radiation. Only if both width and length are zero is there no radiation.