Seung-Hyun Lim

A 2.1 M Pixels, 120 Frame/s CMOS Image Sensor With Column-Parallel

This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 e_rms^- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e^-·nJ.

\Delta \Sigma

Vertical NAND (VNAND) technology relies on polysilicon for channel material. Two intrinsic variation sources of the cell threshold voltage induced by polysilicon traps have been identified and simulated: Random Trap Fluctuation (RTF) and Random Telegraph Noise (RTN). We demonstrate that RTN is enhanced by the polysilicon material and an original model explains the asymmetric RTN distribution observed after endurance. This work enables the prediction of VT distribution for VNAND devices in MLC operation.

ADC Architecture

This paper proposes a low-power 240 frames/s 2.1 M-pixel CMOS image sensor with column-shared cyclic (CY) ADCs. Two-column shared CY-ADC architecture and two-level stacked ADC placement are employed for low-power and small pixel pitch design. The proposed CY-ADC uses only one OTA and four capacitors. Distributed clocking scheme using cascaded repeaters is proposed to reduce the required peak current. The prototype sensor was fabricated in a 0.13- μm 1P4M process with pixel pitch of 2.25 μm . The designed 10-bit ADC dissipates only 90 μW/channel with 1.5 V supply. The measured DNL and INL are +0.59/-0.83 LSB and +2.8/-3.6 LSB, respectively. The measured maximum pixel rate is 500 Mpixels/s with total power consumption of 300 mW.

Intrinsic fluctuations in Vertical NAND flash memories

A novel multi-level charge trap flash memory with band engineering concept on the trap layer is firstly demonstrated. The engineered band structure, Si₃N₄/Al₂O₃/Si₃N₄ (NAN) was adopted as a trap layer in place of single Si₃N₄ layer in TANOS structure (Y. Shin et al., 2005). Compared to the reference structure of single Si₃N₄ trap layer, charge trap flash memory based on NAN trap layer shows larger memory window (~10 V), which is ideal for multi-level application. In addition, highly reliable operation is obtained due to lower program/erase voltages, superior endurance, and smaller room/high temperature pre-/post-cycling charge loss (DeltaVth <0.5 V).

A 240-frames/s 2.1-Mpixel CMOS Image Sensor With Column-Shared Cyclic ADCs

The demand for high-quality and high-speed imaging has increased. Column-parallel ≥14b A/D conversion is one of the major approaches to meet these requirements in CMOS image sensors (CIS). Oversampling ADCs such as incremental delta-sigma (I-ΔΣ) ADCs are the solution for a high-resolution ADC having tolerance of analog component errors. Oversampling reduces input temporal noise as well as the quantization error of the ADC itself [1]. However, an I-ΔΣ ADC is also classified as a slow ADC because it requires exponential conversion time to get higher bit resolution. To reduce conversion time, there are two alternative methods: 1) higher-order modulation, and 2) two-step conversion such as an extended-counting technique [2]. In this paper, the extended-counting (EC) method is used since a high-order structure requires more complex hardware and greater power consumption [1,2]. For a general two-step ADC, coarse conversion restricts the total ADC resolution since it determines accuracy of the residue. However, an EC ADC overcomes the accuracy limitation, since the I-ΔΣ can improve its precision through oversampling. Moreover, oversampling also suppresses the noise of the pixels source follower. Our 14b EC ADC is a blend of a 1st-order I-ΔΣ ADC and a cyclic ADC to simultaneously get high resolution and high speed.

Band Engineered Charge Trap Layer for highly Reliable MLC Flash Memory

A human eye has the logarithmic response over wide range of light intensity. Although the gain can be set high to identify details in darker area on the image, this results in saturation in brighter area. The gamma correction is essential to fit the human eye. However, the digital gamma correction degrades image quality especially for darker area on the image due to the limited ADC resolution and the dynamic range. This paper proposes a CMOS image sensor (CIS) with nonlinear analog-to-digital converter (ADC) which performs analog gamma correction. The CIS with the proposed nonlinear ADC conversion scheme was fabricated with a 0.35-mum CMOS process. The test results show the improved image quality than digital gamma correction

A 14b extended counting ADC implemented in a 24Mpixel APS-C CMOS image sensor

We have investigated thin film transistors (TFTs) with ultra-thin polycrystalline silicon (poly-Si) of 77 Å – 185 Å. The TFT charge transfer characteristics such as ON current and effective mobility are dominated not by the thickness itself but by the grain size of poly-Si channel. When the poly-Si channel thickness is decreased with the same grain size, the sub-threshold TFT characteristics are improved without degradation of ON current and reliability properties. These results give us appropriate criteria to establish an excellent poly-Si channel in vertical NAND flash memory.

CMOS image sensor with analog gamma correction using nonlinear single-slope ADC

We describe a novel technique of fabricating WN nanocrystal memory device. Pulsed nucleation layer (PNL) method is firstly introduced for the formation of uniformly distributed high density (/spl sim/ 1.6 /spl times/ 1012 /cm/sup 2/) nanocrystals with the size of 3 /spl sim/ 5 nm. The WN nanocrystal memory exhibits very large threshold voltage shifts over 3.5 V and good retention and endurance characteristics. Further improvement of memory performances using stacked tunnel barrier and double layer storage node structures was also presented.

Investigation of ultra thin polycrystalline silicon channel for vertical NAND flash

In this work, we propose a MHSOS (metal gate/high-k/SRO(silicon-rich oxide)/SiO2/Si) structure showing large memory window (> 4V) with fast P/E speed (plusmn18 V, 200 mus). The erase speed is featuring faster than that of Si3 N4 and has a retention time of 10 years for 10 % charge loss. These excellent properties were obtained through the modification of the transition layer between Si-NC and SiO2 matrix in an SRO medium, as well as tunneling/blocking dielectric material optimization

Nonvolatile MOSFET memory based on high density WN nanocrystal layer fabricated by novel PNL (pulsed nucleation layer) method

Data retention characteristics of aggressively scaled high-k interpoly dielectrics (IPD) with a fully planar stacked cell are thoroughly investigated. Using high temperature retention experiments of devices programmed at threshold voltages comparable to those used for multi-level cell (MLC) operation and reduced equivalent oxide thicknesses (EOT), we show that retention behavior simply depends on the electric field across the IPD, which is in quadratic inverse proportion to the IPDs reduced EOT. In order to overcome the scaling limits guaranteeing the memory cells reliability, we propose a new high-k stack without the bottom oxide and achieve excellent reliability, less than 0.3V of charge loss with IPD EOT below 7nm. Based on a trap-assisted tunneling model, we simulate the charge loss behavior through the high-k IPD and pave the way for further reducing the IPD EOT to realize memory cells with feature sizes beyond sub-30nm.