Seog Moon Choi

Silicon-Based, Multi-Chip LED Package

A new silicon based multi chip white LED PKG for high power application is designed, fabricated and tested. The package is composed of Al layer coated reflector cup, silicon base which has micro through via hole for interconnection, and micro lens. Compared to the most conventional single chip LED PKG, multi chip white LED PKG has many advantages in cost, density, size, thermal resistance and optical efficiency. After numerical analysis, silicon based multi chip LED PKG which has 9 mm times 9 mm with 0.65 mm size is fabricated using simple MEMS technology. The thermal resistance of this new silicon package was about 4-5 K/W from junction to case in simulation and this result could be comparable to that of other high power LED package. Also, this PKG platform has over than 60% increase in optical extraction efficiency. The proposed multi chip LED PKG can find applications, such as a next generation solid state lighting, back light units and etc.

6B-6 An Ultra Small SAW RF Filter using Wafer Level Packaging Technology

Since a multitude of surface acoustic wave (SAW) filters are the key components for wireless communications, they play an important role in todays mobile phone evolution. Increasing the levels of functional integration and size reduction are therefore the major driving forces in recent SAW radio frequency (RF) filter development. This paper presents a pioneering work for design and fabrication of ultra small SAW filter package. A novel wafer level packaging technology based on through-wafer interconnection and wafer-to-wafer bonding is designed to achieve highly miniaturized SAW RF filters. Based on this technology, SAW RF filters for mobile phone systems are developed in the worlds smallest size of 1.0 times 0.8 times 0.25 mm3. It is shown that our newly developed SAW RF filter offers equal frequency characteristics compared with the conventional chip-sized package. And the reliability test result of hermetically sealed SAW filter package will be presented to verify its application to mobile phones. As a result of these developments, wafer-level packaged SAW RF filters will offer considerable advantages over conventional chip-sized packages in many aspects of performance and production, including size, cost, and further integration

Reflowable ISM WLP

A new ISM (image sensor module) WLP (wafer level package) for reflow process is designed, fabricated and tested. The proposed ISM WLP is composed of polymer bonding layer, glass cap wafer for particle free process and CIS (CMOS Image Sensor) chip wafer which has micro via hole interconnection. During the last decades, WLP is highlighted as the next generation ISM Package method for many advantages like high yield (particle free process), small form factor (3D interconnection), low assembly cost and so on. Nevertheless these benefits, there are some difficulties like micro via hole fabrication, low temperature insulation process (inside hole), bottom side oxide etching process, warpage control according to wafer level bonding using different material, and whole process temperature limitation for micro lens damage. Among various fabrication methods for ISM package, COB (Chip on board), COF (Chip on film), and L, T contact WLP from ShellCase are generally used. In case of COB and COF package, it has difficulty in particle control during assembly process. In case of ShellCase type WLP has very complicated fabrication process. Additionally, most of above package has disadvantage in size point of view. Through suggested ISM WLP using thru interconnection via is realized. And we can good photo image using fabricated WLP. It can not only solve problems of conventional packaging structures but also tremendously reduce the manufacturing & assembly cost (include time) of ISM package and realize real chip scale package.

Aluminum Packaging for Light-Emitting Diode using Selectively Anodizing Method

By the development of a high-power light-emitting diode (LED) for solid state lighting, the demand for driving current has increased rapidly, thereby increasing power dissipation. The heat flux corresponding to power dissipation is mainly generated in the p–n junction of LED; thus, the effective removal of heat is the most important function of LED packaging for increasing the lifetime of a LED chip. In this study, we proposed an aluminum packaging for a high-power LED using selectively anodizing technology and simulated its heat dissipation characteristic. Our aluminum packaging structure is composed of a reflector and an electrical via in one aluminum body. The reflector was fabricated by isotropic chemical etching and the electrical via was formed by selectively anodizing in the same body. The heat generated from the LED chip was directly dissipated through the entire aluminum body. Our aluminum packaging platform can easily be expanded into an array and wafer-level package. Thus, it is suitable for high-efficiency and low-cost packaging.

Miniaturization and Optimization of RF SAW Filter Using Wafer Level Packaging Technology

In this paper, we describes the wafer level surface acoustic wave (SAW) filter package, 1.0times0.8 mm2, which is applicable for radio frequency (RF) stage in mobile phones. The SAW filter is reduced in size and thickness by using a 4 wafer level package process technique. The technique uses interconnection via and LiTaO3 (LT)-LiTaO3 (LT) wafer bonding structure. The interconnection via is formed through LT wafer by using sand blasting or laser drilling method. The AuSn eutectic bonding enables the connection of the signal pad on the SAW chip, with gold metallized LT wafer package. This eutectic bonding ensures that the SAW chip is protected mechanically and connected electrically, with the package. In order to simulate and optimize the structure and characteristics of wafer level SAW filter package, we used HFSS and ADS software. Frequency responses of measurement and simulation are compared with wafer level SAW filter package. The results of reliability tests for wafer level SAW filter package will be discussed.

Development of lamination process for chip-in-substrates

Fiber-reinforced composites are used as insulating layers in PCBs to reduce thermal residual stress and warpage due to their low coefficient of thermal expansion (CTE) and high elastic modulus. The composite prepreg is laminated on patterned copper layers by hot-press molding process to apply temperature and pressure cycles. In this study, the lamination process of glass/epoxy woven composite in the chip- embedded PCB was investigated in order to manufacture reliable chip-embedded PCB. Temperature profiles in several panels stacked in the hot-press were measured to estimate degree of cure and resin-fill characteristics. The degree of cure was evaluated by a cure kinetic model constructed from dynamic and isothermal differential scanning calorimetry (DSC), while the resin flow through via holes and around embedded chips was analyzed by a viscosity model constructed from isothermal rheometry.

Rectangular Microlens Array Having High Sag for Multi Chip LED Packaging

A novel rectangular shape microlens array having high sag for solid-state lighting is presented. The rectangular shape of proposed microlens can maximize the fill factor of silicon based light-emitting-diode (LED) packaging and minimize the optical loss through the reduction of unnecessary reflection at the same time. Microlens, which has high sag, over 3 75 μm and large diameter, over 3 mm can enormously enhance output optical extraction eff iciency. Moreover wafer level packaging technology is adopted to improve the aligning accu racy and mass production of LED packaging. This wafer level microlens array can be direc tly fabricated on LED packaging using replication method. It has many advantages in optica l properties, low cost, high aligning accuracy, and mass production.

Wafer Level Bonding for LED Packaging Using Six Sigma Methodology

As Recently, wafer level packaging (WLP) received lots of attention in system because it shows the potential to reduce packaging cost, while the yield of devices after dicing and packaging can be increased. In this study, we newly proposed WLP for light emitted diodes (LED) using MEMS technology. Our silicon package structure is composed of base and reflector cup. The role of base is that settle LED chip at desired position and supply electrical interconnection for LED operation. Reflector cup was formed by an-isotropic wet etching. Package platform could be fabricated by eutectic bonding between base and reflector cup using AuSn. We carried out process using six sigma methodology. We first decided 2 factors and 3 levels by design of experiment (DOE). One factor is the kind of metal model. The other is the shape of pattern. It was used that three-kind metal models are Au (cup), AuSn (cup), and AuSn (base). The bonding strength is measured using a die shear strength tester. It carried out in the repetition experiment by a unit of 3 times. As a result of this test, the AuSn(base) metal model and the No.3 pattern were applied by the optimal condition. We set the value of the low limit at shear strength 950g/mm2 for applying sigma level. This value is a generally used for eutectic bonding packages. The experiment results have 3.13 sigma level (95% yield). In this paper, We show the final LED package which is finished up to LED attach, wire bonding, encapsulation, etc. This wafer level bonding process demonstrates its promising potential at the wafer level packaging in LED packaging.

Large Displacement Out-Of-Plane Bimorph Actuator for Optical Application

A new thermal bimorph actuator for large out-of-plane displacement is designed, fabricated and tested. The deflecting beam is composed of polyimide, heater, and polyvinyl difluorides with tetrafluoroethylene (PVDF-TrFE). The large difference of coefficient of thermal expansion (CTE) of two polymer layers (polyimide and PVDF-TrFE) can generate a large deflection with relatively small temperature rising. Compared to the most conventional micro actuators based on MEMS (micro-electro mechanical system) technology, a large displacement, over 1 mm at 20 mW, could be achieved. The proposed actuator can find applications where a large vertical displacement is needed while keeping compact overall device size, such as a micro zooming lens, micro mirror, micro valve and optical application.

Interconnection via technology and wafer level package for crystal unit device

Most important technology for developing of wafer level packaging is studied in this paper. That is the process of drilling the via hole that are needed filling of conductive material for electrical connection or non-conductive material for reliability. Several kinds of drilling and filling methods of via holes for the interconnection were studied. The via formation for interconnection is based on smaller and lower cost package process. However, glass wafer which is substrate material of wafer level package for crystal unit device is difficult to make via by using novel method. The structure of wafer level crystal unit package for low cost and high performance is designed and optimized. The glass and Si wafer for package substrate and lid is chosen and considered as the structure for its mechanical and thermal strength and effective process of mass production. The interconnection via is formed through glass wafer by using sand blasting or laser drilling and Cu electro-plating method that enable the connection of the signal electrode on the quartz blank. The interconnection via process for wafer level crystal unit package with 2.0×1.6×0.45 mm3 size and results of electrical performance is evaluated.