Seok-Bong Hyun

A 6.3-9-GHz CMOS fast settling PLL for MB-OFDM UWB applications

A CMOS phase-locked loop (PLL) which synthesizes frequencies between 6.336 and 8.976 GHz in steps of 528 MHz and settles in approximately 150 ns is presented. The proposed PLL can be employed as a building block for a frequency synthesizer which generates a seven-band hopping carrier for multiband orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) radio. To achieve fast loop settling, integer-N architecture that operates with 528-MHz reference frequency is implemented and a wideband active-loop filter is integrated. An improved phase-frequency detector (PFD) is proposed for faster loop settling. To reduce reference sidebands, a feedback circuit using replica bias is implemented in the charge pump. I/Q carriers are generated by two cross-coupled LC VCOs. The output current of the charge pump is controlled to compensate for the VCO gain nonlinearity and a programmable frequency divider (12/spl les/N/spl les/17) that reliably operates at 9 GHz is designed. Fabricated in 0.18-/spl mu/m CMOS technology, the PLL consumes 32 mA from a 1.8-V supply and achieves phase noise of -109.6dBc/Hz at 1-MHz offset and spurs of -52 dBc.

Low power high linearity transmitter front-end for 900 MHz Zigbee applications

This paper presents a low power high linearity transmitter front-end for 900 MHz Zigbee applications based on 0.18 mum CMOS technology. The direct up-conversion is implemented by passive mixer which dissipates no DC current. Two stage driver amplifiers provide high enough gain as well as high linearity to drive high power signal to 50Omega antenna while consuming small amount of current. Measurement shows 11.5 dB overall transmitter gain, 3 dBm output P1dB while dissipating 1.8mA DC current from 1.8 V supply

Current reuse cross-coupling CMOS VCO using the center-tapped transformer in LC tank for digitally controlled oscillator

A current reuse cross-coupling transformer-based VCO with low phase noise and low power consumption was implemented in 0.13 mum CMOS. The oscillation frequency was tuned from 4.6 GHz to 6 GHz (26% tuning range) using two different-sized varactor that adjusted fine and coarse tuning. The measured phase noise at 5.0 GHz was -124 dBc/Hz (1 MHz offset) and maximum output power level was -5.5 dBm. The 0.4times0.3 mm2 core consumes very low power of 1.8 mW for 1.2 V and FOM has -196.2 dB.

A direct-conversion receiver for low-voltage low-power multi-band UWB with a novel single-level mixer

A CMOS direct-conversion receiver including a low noise amplifier and a novel single transistor stacked mixer is proposed in this paper. The LNA has a small signal gain of 12-10 dB and a noise figure of 4.2-4.8 dB in 3-7 GHz range. The conversion gain and the input P1dB of the mixer are 3-6.5 dB and -10 dBm, respectively with the multiband RF signals. The LNA consumes 9.2 mA and the mixer consumes 4.3 mA under 1.8 V supply voltage, respectively

PWM based CMOS supply modulator for LTE envelope tracking transmitter

A PWM based supply modulator on 180nm CMOS process for a high efficiency envelope tracking transmitter is designed. For high efficiency PWM operation, a ramp generator and a non-overlap clock generator are used. With an LTE 20MHz envelope signal with 7.6dB PAPR, the supply modulator shows efficiency of 72.2% with a resistive load of 2ohm.

Power Breakdown Analysis of a WCDMA Handset with Multi-channel Power Monitoring System

Monitoring power consumption of a running system is a first step to determine where to take an effort on power optimization to minimize unnecessary idle time in available operation modes. Coordinating hardware and software architecture in a certain block or module to extend its lifetime requires system-wide power breakdown profiling, which then validates applicable power saving techniques because of a trade-off between cost and benefit. Experimental results show that with a commercial 3G WCDMA handset, a multi-channel power monitoring system gathers real-time traces of power consumption of the WCMDA MSM6250 chipset platform under several different conditions, and generates comprehensive power breakdown analysis to verify power saving techniques.

Design of CMOS continuous-time low-pass delta-sigma modulator for digital distributed antenna system based on IF-over-fiber transmission

A CMOS continuous-time low-pass delta-sigma modulator (DSM) circuit that digitizes an analog mobile signal at 10 MHz intermediate frequency (IF) in a digital distributed antenna system (DAS) with IF-over-fiber scheme is designed in this paper. Detailed design processes and results from system to circuit levels are provided, which is helpful for the design of a DSM circuit for another digital DAS system based on DSM technique. The simulated peak signal-to-noise and distortion ratio of the designed DSM circuit was 49.4 dB, and high stop-band rejection ratios were achieved by exploiting the zero optimization technique in the noise transfer function of the designed DSM.

A Dual-Channel 6b 1GS/s 0.18um CMOS ADC for Ultra Wide-Band Communication Systems

This work proposes a dual-channel 6b 1GS/s ADC for ultra wide-band communication system applications. The proposed ADC based on a 6b interpolated flash architecture employs wide-band open-loop track-and-hold amplifiers, comparators with a wide-range differential difference preamplifier, latches with reduced kickback noise, on-chip CMOS references, and digital bubble code correction circuits to optimize power, chip area, and accuracy at 1GS/s. The ADC implemented in a 0.18mum 1P6M CMOS technology shows a signal-to-noise-and-distortion ratio of 30dB and a spurious-free dynamic range of 39dB at 1GS/s. The measured differential and integral nonlinearities of the prototype ADC are within 1.00LSB and 1.25LSB, respectively. The dual-channel ADC has an active area of 4.0mm2 and consumes 594mW at 1GS/s and 1.8V

Carrier Cancelling RF for Multi-Mode SDR Terminal Applicable to CDMA-Cellular, WCDMA, and WiBro

The carrier cancelling radio frequency (CCRF) is an important sub-system in the future mobile SDR (software defined Radio) terminal which employing one-step frequency down conversion before analog to digital conversion. The CCRF offers analog IF signal up to 75 MHz to an ADC sampling with 150MS/s and converting analog IF to digital IF signal. In this paper, we propose a 0.13 um CMOS wideband and reconfigurable low noise amplifier, a wideband active balun, a wideband mixer, and a programmable LO which are composing a CCRF for CDMA-Cellular, WCDMA, and WiBro applications.

Low power consumptive mixed mode MMIC power amplifier module for WCDMA handset applications

A high average-efficient MMIC power amplifier is implemented utilizing mixed mode power stage techniques with proper linearity. The average power efficiency, which is more important fact to save the battery in handsets, is improved about three times than commercial PAs with only supply voltage of 3.0-V. The power amplifier has been optimized for different P1 dB (1-dB compression point) value: one for 16 dBm for the low power mode, targeting the most probable transmission power, and the other for 28 dBm for the high power mode. A PAE of 29.0% at 16 dBm of out power, which is the maximum bound of the most probable transmission power in IS-95 systems, was obtained, as well as 46.7% at 28.2 dBm for the high power mode. The measured adjacent channel leakage power ratios (ACLR) at the high and low power mode of PldB are -36.17 and -36.16 dBc, respectively, and satisfy the Third-Generation Partnership Project (3GPP) WCDMA specification.