Seok Kim

A Digitally Controlled Oscillator With Wide Frequency Range and Low Supply Sensitivity

This brief presents a wide frequency range digitally controlled oscillator (DCO) with low supply sensitivity and low power consumption. We propose a compensation scheme employing feedforward inverters to suppress supply noise. Both wide frequency range and fine resolution are obtained using a hierarchical architecture consisting of a coarse delay chain and an interpolator. The proposed DCO was fabricated in a 0.13-μm CMOS process. It successfully eliminates noise components due to supply variation. The phase noise at 1-MHz frequency offset from the carrier frequency of 700 MHz is -106.3 dBc/Hz. The frequency range of the DCO is measured from 320 MHz to 1.25 GHz.

Synthesis of Polystyrene Nanoparticles with Monodisperse Size Distribution and Positive Surface Charge Using Metal Stearates

Polystyrene (PS) nanospheres with a monodisperse size distribution, positive surface charge and high molecular weight were successfully synthesized using various types of metal stearates in an aqueous NaOH medium. The diameter of the PS nanospheres was controlled from 80 to 450 nm by changing the type of metal stearate. It was also found that controlling the NaOH concentration in solution was important for producing monodisperse PS nanoparticles. The nanospheres prepared with zinc stearate possessed a positive surface charge of 60 to 80 mV, confirming that PS particles were functionalized with metal stearates. It is believed that the metal stearates provide PS particles with not only colloidal stability but also a positive surface charge.

A 5.2-Gb/s Low-Swing Voltage-Mode Transmitter With an AC-/DC-Coupled Equalizer and a Voltage Offset Generator

This paper describes a voltage-mode transmitter with an AC-/DC-coupled equalizer. A dual-loop regulator controls the tap-weight coefficient for the DC-coupled equalizer while maintaining the output matching condition. An AC-coupling technique is employed to enhance the edge rate and reduce the burden of the DC-coupled equalizer. The transmitter also supports the ability to add a DC differential voltage offset into the output signal so that the voltage margin of the link can be measured. The transmitter was fabricated using a 0.13-um CMOS technology. When 240- mVPP, 5.2-Gb/s data are sent over 20-inch FR4 channels, the eye of the received data has a voltage margin of 60 mV and a peak-to-peak jitter of 40 ps. The proposed transmitter consumes 5.86 mW from a 1.2-V supply while operating at 5.2 Gb/s.

A low-power dual-PFD phase-rotating PLL with a PFD controller for 5Gb/s serial links

A novel phase rotating PLL with a dual phase frequency detector (PFD) for 5Gb/s serial links is proposed. By employing a PFD controller, the PLL eliminates a fatal error in phase interpolation due to a nondeterministic characteristic of the PFD. It achieves interpolation between two clocks spaced 180° apart, making the overall structure much simpler with low power consumption. The test chip was implemented in a 65-nm CMOS technology. 8 multi-phase clocks can be simultaneously shifted in steps of 25ps, showing both INL and DNL less than half LSB. Its rms jitter is 0.18ps at 1.25GHz and power consumption is only 3mW from a 1.2V power supply.

Design of a Reliable Broadband I/O Employing T-coil

Inductive peaking using T-coils has been widely used in broadband I/O interfaces. In this paper, we analyze technical effects and limitations of the T-coil, and discuss several methods that can overcome these restrictions and improve the practicality of the T-coil. In particular we also propose and verify a circuit topology which can further extend bandwidth beyond the limit that conventional T-coil can achieve, and transfer 20 Gb/s data without noticeable distortion.

A low-swing AC- and DC- coupled voltage-mode driver with pre-emphasis

This paper describes a 2-tap voltage-mode driver with an auxiliary AC-coupled driver. Tap weight control and impedance matching are accomplished by a dual-loop regulator. The AC-coupling technique is employed to enhance the edge rates and reduce the burden of the post-tap equalizer. The proposed transmitter is fabricated using a 0.13-µm CMOS technology. It is shown that when 200mVp-p 5-Gb/s signals are sent over 10″ FR4 channels, the eye of the received data has 0.87 UI timing margin, 114 mV voltage margin.

A 12.5-Gb/s near-GND transceiver for wire-line UHD video interfaces

This paper demonstrates a 12.5-Gb/s complete transceiver with near-ground and voltage-mode signaling. The output stage of the transmitter has two types of equalization methods: 2-tap FIR, AC-coupled equalization. The receiver equalizes the attenuation of the cable with a continuous time linear equalizer which includes a level-up shifter for receiving near-ground input signal. A dual-loop clock and data recovery circuit using a bang-bang phase detector is implemented for a receiver clock generation. The test-chips are fabricated in a 45-nm CMOS technology, and successfully perform data communication through -27 dB loss video cables. The entire transmitter and receiver test-chips respectively consume 92 mW and 138 mW from a 1.2 V supply while operating at 12.5 Gb/s.

A 12.5-Gb/s Near-Ground Transceiver Employing a MaxEye Algorithm-Based Adaptation Technique

A 12.5-Gb/s complete near-ground transceiver is demonstrated. The output stage of the transmitter (TX) employs 2-tap finite-impulse response equalization (EQ) and also performs ac-coupled EQ for an additional EQ. A continuous-time linear equalizer (CTLE) on the receiver (RX) side compensates for the channel attenuation. Based on the maximum eye algorithm, the peaking gain of CTLE is adaptively controlled to track a time-variant environment, such as PVT variations. Each TX and RX is implemented with clocking circuits: a differential PLL, and a dual-loop clock and data recovery circuit. The proposed transceiver is fabricated in a 45-nm CMOS process, and the entire TX and RX, respectively, consume 92 and 138 mW under a 1.2-V supply while operating at 12.5 Gb/s.

A 6.4-Gb/s Voltage-Mode Near-Ground Receiver With a One-Tap Data and Edge DFE

A low-power receiver with a one-tap data and edge decision-feedback equalizer (DFE) and a clock recovery circuit is presented. The receiver employs analog adders for the tap-weight summation in both the data and the edge path to simultaneously optimize both the voltage and timing margins. A switched-capacitor input stage allows the receiver to be fully compatible with near-GND input levels without extra level conversion circuits. Furthermore, the critical path of the DFE is simplified to relax the timing margin. Fabricated in the 65-nm CMOS technology, a prototype DFE receiver shows that the data-path DFE extends the voltage and timing margins from 40 mVpp and 0.3 unit interval (UI), respectively, to 70 mVpp and 0.6 UI, respectively. Likewise, the edge-path equalizer reduces the uncertain sampling region (the edge region), which results in 17% reduction of the recovered clock jitter. The DFE core, including adders and samplers, consumes 1.1 mW from a 1.2-V supply while operating at 6.4 Gb/s.

48 MHz clock generating system for USB 2.0 with enhanced bandgap reference

A clock generating system for USB 2.0 with an enhanced bandgap reference circuit is proposed to replace an external crystal oscillator. To comply with clock frequency and long term jitter specifications under high supply noise, the power supply of the DCO is regulated by a low drop-out regulator. The reference voltage for the LDO is generated by the bandgap reference circuit with two bandgap cores to achieve high PSRR. The proposed clock generating system implemented in a 130nm CMOS process shows ±2.5ns jitter under ±400mV supply noise.