Young Hyun Jun

A 1.2 Gb/s/pin double data rate SDRAM with on-die-termination

For operating frequencies exceeding 500 MHz, the timing margin of the I/O interface is critical and requires the data input-output timing accuracy to be within 200 ps. To meet the requirement, the designed SDRAM adopts a digitally self-calibrated on-die-termination with linearity error of /spl plusmn/1% and achieves over 1.2 Gbps/pin stable operation by using window matching and latency control. The chip is fabricated in a 0.13 /spl mu/m triple-well DRAM process.

A highly reliable multi-cell antifuse scheme using DRAM cell capacitors

A highly reliable antifuse cell and its sensing scheme that can be actually adopted in DRAM are presented. A multi-cell structure is newly devised to circumvent the large process variation problems of the DRAM cell capacitor type antifuse system. The programming current is less than 564µA up to the nine-cell case. The experimental results show that the cumulative distribution of the successful rupture in multi-cell structure is dramatically enhanced to be less than 15% of single-cells case and the recovery problem of the programmed cell after the thermal stress (300°C) is disappeared. In addition, also presented is a Post-Package Repair (PPR) scheme that is directly coupled to external power using additional pin for the requisite high voltage with protection circuits, saving the chip area otherwise consumed by the internal pump circuitry. A 1Gbit DDR SDRAM is fabricated using Samsungs advanced 50nm DRAM process technology, successfully showing the feasibility of the proposed antifuse system implemented in it.

A pre-emphasis output buffer control scheme for a GDDR3 SDRAM interface

The keys to good signal integrity in a Graphic DDR3 (GDDR3) SDRAM interface for a bandwidth up to 1.4Gbps/pin are the minimization of input/output pin capacitance and the accurate control of the output data skew. The proposed pre-emphasis output buffer control scheme provides output data skew minimization without an increase of input/output pin capacitance. Compared to the conventional scheme, the output data aperture window of proposed scheme has increased by 18% and the data output skew has decreased by 48%.