Seok-Yoon Kim

Short circuit power estimation of static CMOS circuits

This paper presents a simple method to estimate short-circuit power dissipation for static CMOS logic circuits. Short-circuit current expression is derived by accurately interpolating peak points of actual current curves which is influenced by the gate-to-drain coupling capacitance. It is shown through simulations that the proposed technique yields better accuracy than previous methods when signal transition time and/or load capacitance decreases, which is a characteristic of the present technological evolution.

A new scheduling technique based on Dynamic Voltage Scaling for MPSoC

The DVS(Dynamic Voltage Scaling) technique is the method to reduce the dynamic energy consumption. Using slack times, it extends the execution time of big load operations by changing frequency and voltage of variable voltage processors. Many researches have been going on to control the energy consumption of the processors and the data transmission among processors by controlling the bandwidth to reduce the energy consumption of the entire system. Since operations in multiprocessor systems have the data dependency between processors, however, the DVS techniques devised for single processors are not suitable to improve the energy efficiency of multiprocessor systems. We propose a new scheduling algorithm based on DVS for increasing energy efficiency of multiprocessor systems. The proposed DVS-based scheduling algorithm can improve the energy efficiency of entire systems because it controls frequency and voltages while considering the data dependency among processors.

An analytic calculation method for delay time of RC-class interconnects

This paper presents an analytic 3rd order calculation method, without simulations, for delay time of RC-class circuits, which can be conveniently used to model on-chip interconnects. While the proposed method requires comparable evaluation time to the previous 2nd order calculation method, it ensures more accurate results than those of 2nd order method. The proposed analytic delay calculation method guarantees allowable error tolerance when compared to the results obtained from the AWE technique or HSPICE and has better performance in evaluation time as well as numerical stability. The first algorithm of the proposed method requires 7 moments for the 3rd order approximation and yields accurate delay time approximation. The second algorithm requires 5 moments for the 3rd order approximation and results in shorter evaluation time, the accuracy of which may be less than the first algorithm.

Low-power dynamic scheduling algorithm For real-time multiprocessor systems

DVS(dynamic voltage scaling) is one of the important low-power techniques. To reduce power consumption, lowering the voltage of active tasks using the idle time of a processor increases processing time by reducing the frequency. But hard real-time systems under strong time constraints need the powerful multiprocessors which can execute tasks in a fixed time. Therefore the latest embedded systems require high performance as well as minimum power consumption. This paper proposes the GMD(greedy myopic-based DVS) algorithm. The GMD algorithm satisfies time constraints of real-time multi-processor systems and low-power design, as applying DVS to the myopic algorithm based on the heuristic function for the dynamic scheduling of tasks have time constraints and resource requirements. While the GMD algorithm yields a performance similar to that of myopic algorithm, it can also reduce the power consumption of multiprocessor systems.

The Improvement in Signal Integrity of FT-ICR MS

For efficient noise reduction in a Fourier transform ion cyclotron resonance (FT-ICR) mass spectrum, a new algorithm was proposed. The suggested algorithm reduces white and electrical noise, and it improves signal-to-noise ratio. This algorithm has been optimized to reduce the noise more efficiently using the traces of signal level. The algorithm has been efficiently combined with derivative window to improve the resolution as well S/N. Time domain data was corrected for DC voltage interference. window was applied in time domain data to improved the resolution. However, window can improve the signal resolution, it will also increase the noise level in frequency domain. Therefore, newly developed noise reduction algorithm will be applied to make a balance between resolving power and S/N ratio for magnitude mode. The trace algorithm can determine the current data point with several data points (mean, past data, calculated past data). In the current calculations, we assumed data points with S/N ratio more than 3 were considered as signal data points. After the windowing and noise reduction, both resolution and signal-to-noise ratio were improved. This algorithm is applicable more efficiently to frequency dependent noise and large size data.For efficient noise reduction in a Fourier transform ion cyclotron resonance (FT-ICR) mass spectrum, a new algorithm was proposed. The suggested algorithm reduces white and electrical noise, and it improves signal-to-noise ratio. This algorithm has been optimized to reduce the noise more efficiently using the traces of signal level. The algorithm has been efficiently combined with derivative window to improve the resolution as well S/N. Time domain data was corrected for DC voltage interference. tⁿ window was applied in time domain data to improved the resolution. However, tⁿ window can improve the signal resolution, it will also increase the noise level in frequency domain. Therefore, newly developed noise reduction algorithm will be applied to make a balance between resolving power and S/N ratio for magnitude mode. The trace algorithm can determine the current data point with several data points (mean, past data, calculated past data). In the current calculations, we assumed data points with S/N ratio more than 3 were considered as signal data points. After the windowing and noise reduction, both resolution and signal-to-noise ratio were improved. This algorithm is applicable more efficiently to frequency dependent noise and large size data.

RMS Current Estimation Technique for Reliability Analysis of Multiple Semiconductor Interconnects

As process parameters scale, interconnect width are reduced rapidly while the current flowing through interconnects does not decrease in a proportional manner. This effect increases current density in metal interconnects which may result in poor reliability. Since RMS(root-mean-square) current limits are used to evaluate self-heating and short-time stress failures caused by high-current pluses, RMS current estimation is very important to guarantee the reliability of semiconductor systems. Hence, it is critical to estimate the current limits through interconnects earlier in semiconductor design stages. The purpose of this paper is to propose a fast, yet accurate RMS current estimation technique that can offer a relatively precise estimate by using closed-form equations. The efficiency and accuracy of the proposed method have been verified through simulations using HSPICE for a vast range of interconnect parameters.

A delay estimation method using reduced model of RLC interconnects

This paper proposes a new method for delay time calculation in RLC interconnects. This method is simple, yet precise. The proposed method can calculate the delay time of RLC interconnects by simple numerical formula calculation without complex moment calculation using reduced model RLC interconnects. The results using the proposed method for RLC circuits show that the average relative error is within 10% in comparison with HSPICE simulation results.

An efficient delay metric on RC interconnects under saturated ramp inputs

This paper presents a simple and fast delay metric RC-class interconnects under step and saturated ramp inputs. The proposed RC delay metric under step input, called MECM(Modified ECM), provides a reasonable accuracy without using circuit moments. The next RC delay metric under saturated ramp inputs, called FDM(Fast Delay Metric), can estimate delay times at an arbitrary node using a simple closed-form expression and is extended from MECM easily. As compared with similar techniques proposed in previous researches, it is shown that the FDM technique involves much lower computational complexity for a similar accuracy. As the number of circuit nodes increases, there will be a significant difference in estimation times of RC delay between the previous techniques based on two circuit moments and the FDM which do not depend on circuit moments.

An Efficient Estimation Method of Dynamic Power Dissipation on VLSI Interconnects

Up to the present, there have been many works to analyze interconnects on timing aspects, while less works have been done on power aspects. As resistance of interconnects and rise time of signals decrease, power dissipation associated with interconnects is ever-increasing. Hence, an efficient method to compute power dissipation on interconnects is necessary and in this paper we propose a simple yet accurate method to estimate dynamic power dissipation on interconnects. We propose a new reduced-order model to estimate power dissipation on large interconnects. Through the proposed model which is directly derived from total capacitance and resistance of interconnects, we show that the dynamic power dissipation on whole interconnects can be approximated, and propose an analytic method to compute the power dissipation. The results of the proposed method applied to various RC networks show that maximum relative error is within 7% in comparison with HSPICE results.