Seong-Ho Park

Yield enhancement with DFM

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

Steady state analysis of timed event graphs with time window constraints

For discrete event systems, time window constraints between two events are often required to control their behavior. Such time constrained discrete event systems are found in various industrial systems such as chemical vapor deposition processes for wafer fabrication, electroplating lines for printed circuit board fabrication, microcircuit design etc. A negative event graph (NEG) which is an extension of the timed event graph (TEG) has been proposed by Lee and Park (2005) to model and analyze discrete event systems with time window constraints. An NEG can model time window constraints between any two transitions by introducing negative places and negative tokens. This study examines the steady state behavior of an NEG that satisfies the time window constraints. We develop a recurrent equation for the feasible steady firing epochs based on the minimax algebra. In addition, we identify four classes of steady states that correspond to the earliest and latest feasible steady firing schedules for each of the minimum and maximum cycle times by extending the steady state results of a conventional TEG based on the minimax algebra. Besides, we characterize how the cycle times and the steady schedules are computed through the matrix algebra and the associated graph algorithms.

RF characterization of deep-submicron DRAM-embedded CMOS process

In this paper rf characteristics of a 0.25 /spl mu/m DRAM embedded CMOS process, focused on the n-MOSFET and the spiral inductor of the critical devices in rf CMOS circuit design, have been investigated. An extremely high cutoff frequency of 44 GHz, high maximum operating frequency of 29 GHz, and a de-embedded minimum noise figure of 1.0 dB have been obtained for a 0.24 /spl mu/m n-MOSFET. As for the spiral inductors, we obtained a peak quality factor of 5.2 at 3.6 nH for a 5-turn inductor and also an inductance of 1.2 to 22.6 nH for inductors with various numbers of turns. These figures of merit seem to be suitable for rf circuits with operating frequency up to 2.5 GHz although the low quality factor of the spiral inductor should be improved.

Development of 0.5 /spl mu/m BiCMOS device model library for RFIC applications

In this paper a 0.5 /spl mu/m BiCMOS device model library developed for RFIC applications has been introduced. The modeling methodology, the RF device characteristics available in this library, their equivalent circuit models with high-frequency parasitics, and modeling results have been described.