Dae-Wook Kim

A Unified Statistical Model for Inter-Die and Intra-Die Process Variation

An efficient characterization technique with the spatial correlation matrix from electrical device parameters such as threshold voltage and saturation current accounting for inter- and intra-die variations is demonstrated. Then, a unified statistical model based on the correlation matrix is developed and implemented to the SPICE simulator to predict the distribution of circuit performance. In order to verify our model, test chips which consist of transistors and ring oscillators were fabricated using a 130nm CMOS technology. Simulated delay/skew variations of ring oscillators agree well with the measurement of test chips, maintaining a reasonable accuracy of 85 %. Especially, we show that as the distance of the two ring oscillators becomes larger, the timing skew between them becomes bigger. Moreover, the sensitivity analysis for the performance of simple analog and digital circuit, is performed in terms of inter-and intra-die variation.

Yield enhancement with DFM

A set of design for manufacturing (DFM) techniques have been developed and applied to 45nm, 32nm and 28nm logic process technologies. A noble technology combined a number of potential confliction of DFM techniques into a comprehensive solution. These techniques work in three phases for design optimization and one phase for silicon diagnostics. In the DFM prevention phase, foundation IP such as standard cells, IO, and memory and P&R tech file are optimized. In the DFM solution phase, which happens during ECO step, auto fixing of process weak patterns and advanced RC extraction are performed. In the DFM polishing phase, post-layout tuning is done to improve manufacturability. DFM analysis enables prioritization of random and systematic failures. The DFM technique presented in this paper has been silicon-proven with three successful tape-outs in Samsung 32nm processes; about 5% improvement in yield was achieved without any notable side effects. Visual inspection of silicon also confirmed the positive effect of the DFM techniques.

Evaluating the effects of physical mechanisms on the program, erase and retention in the charge trapping memory

In this work, a new efficient simulation method with comprehensive physical models is developed to evaluate the performance of CTM at various biases, temperatures, and gate stack configurations. The dominant physical mechanisms on the P/E/R operations of CTM are clarified.

Sensing Margin Analysis of MLC Flash Memories Using a Novel Unified Statistical Model

A multilevel level cell (MLC) technique for flash memories reduces the bit cost and enhances the memory density. However, it is difficult to get a required sensing margin for MLC due to the need for the tight threshold voltage control. We present a unified statistical model which can account for inter-and intra-die variations. The proposed model is implemented into SPICE to predict the distribution of performance. The sensing margin is found to increase by about 30% with optimization of sensitive transistors in the sense amplifier and high voltage regulator. The statistical optimization methodology is essential to achieve an optimal sensing margin and it is widely used for other products such as DRAM, SRAM, DDI and CIS

Statistical approach to design DRAM bitcell considering overlay errors

Overlay performance and control requirements have become crucial for achieving high yield and reducing rework process. Increasing discrepancy between hardware solutions and overlay requirements, especially in sub-40nm dynamic random access memory (DRAM) devices, motivates us to study process budgeting techniques and reasonable validation methods. In this paper, we introduce a SMEM (Statistical process Margin Estimation Method) to design the DRAM cell architecture which considers critical dimension (CD) and overlay variations in the perspectives of both cell architecture and manufacturability. We also proposed the method to determine overlay specifications. Using the methodologies, we obtained successfully optimized sub-40 DRAM cells which accurately estimated process tolerances and determined overlay specifications for all layers.

Local accumulated free carriers in charge trapping memory

The effects of local accumulated free carriers on CTM cells performance are investigated by numerical simulation. Simulation results indicates that local accumulated free carriers do not affect programming and erasing characteristic, however, they are important to CTMs retention characteristic, especially in low threshold state. For CTM cell with thick tunneling oxide and shallow trap depth in charge storage layer, absence of accumulated carriers will underestimate retention capability considerably.