Serge Ecoffey

A damascene platform for controlled ultra-thin nanowire fabrication.

This paper presents a damascene process for the fabrication of titanium micro/nanostructures and nanowires with adjustable thickness down to 2 nm. Their depth is precisely controlled by chemical-mechanical planarization together with in-process electrical characterization. The latter, in combination with a model of the titanium resistivity versus thickness, allows control of the metal line depth in the nanometer range. In summary, we have developed a planarization end point detection method for metal nanostructures. In addition, the model adopted covers geometrical influences like oxidation and ageing. The fabricated titanium nanowire test structures have a thickness ranging from 2 to 25 nm and a width ranging between 15 and 230 nm.

Tunnel Junction Engineering for Optimized Metallic Single-Electron Transistor

The development of metallic single-electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions (TJs). These TJs should insure high-ON current, low-OFF current, and low capacitance. We propose an engineered TJ based on multidielectric stacking. A number of high-k and low-k materials were considered to optimize the TJs characteristics. The optimized TJ is proven to increase the ION current and the ION/IOFF ratio in a double-gate SET. Using TiO2 plasma oxidation and Al2O3 atomic layer deposition, an SET proof of concept, with a double layer TJ, was fabricated and characterized.

Highly transparent low capacitance plasma enhanced atomic layer deposition Al2O3-HfO2 tunnel junction engineering

The development of metallic single electron transistor (SET) depends on the downscaling and the electrical properties of its tunnel junctions. These tunnel junctions should insure high tunnel current levels, low thermionic current, and low capacitance. The authors use atomic layer deposition to fabricate Al2O3 and HfO2 thin layers. Tunnel barrier engineering allows the achievement of low capacitance Al2O3 and HfO2 tunnel junctions using optimized annealing and plasma exposure conditions. Different stacks were designed and fabricated to increase the transparency of the tunnel junction while minimizing thermionic current. This tunnel junction is meant to be integrated in SET to enhance its electrical properties (e.g., operating temperature, I ON/I OFF ratio).

Single Electron Transistor analytical model for hybrid circuit design

A novel analytical and compact model of Single Electron Transistor (SET) is developed and implemented in Verilog-A language for use in hybrid SET-CMOS logic circuit design. The model is based on the steady state Master-Equation (ME). The implementation of this original and simple model, taking into account physical characteristics of tunnel junctions and the thermionic emission, has faithfully reproduced the behavior of metallic SET operating at room temperature. The hybrid SET-CMOS universal logic gate cell is analyzed to illustrate the efficiency of this compact SET model.

Single electron CMOS-like one bit full adder

This paper presents a comparative study of a one-bit-full-adder cell based on metallic complementary capacitively coupled single-electron transistors with its 22 nm CMOS counterpart. Performance and energy efficiency are investigated. The CMOS-like single-electron transistor based full adder is used in two operating mode, hysteresis and non-hysteresis. Parallel and serial single electron transistors designs are introduced. The single electron inverter consumes less than 90.4 pW while it dissipates 4.21 nW in CMOS technology.

A manufacturable process for single electron charge detection, a step towards quantum computing

This paper presents the fabrication, electrical characterization, and simulation of planar single electron transistors. Two single electron transistors facing each other have been used to demonstrate single charge detection. The manufacturable fabrication process combined with both single charge detection and the simulation tool are a powerful platform for quantum cellular automata that can be applied for interfacing classical computing with future quantum computing.

Damascene planar metal-insulator-metal tunnel junctions

In this paper, we show a process for the fabrication of planar sub-attofarad capacitance metal-insulator-metal tunnel junctions with nanometer size. We show the engineering of the material stack, anti-diffusion barrier and electrode metal as well as the result of improved characteristics and stability in time of the devices. This engineering is supported by a simulation tool we developed and its goal is to optimize the original process for the development of high-temperature operating SETs and other innovative nanoelectronic devices.

RECENT DEVELOPMENTS ON 3D INTEGRATION OF METALLIC SET ONTO CMOS PROCESS FOR MEMORY APPLICATION

This work presents a nanodamascene process for a CMOS back-end-of-line fabrication of metallic single electron transistor(SET), together with the use of simulation tools for the development of a SET SRAM memory cell. We show room temperature electrical characterizations of SETs fabricated on CMOS with relaxed dimensions, and simulations of a SET SRAM memory cell. Using their physical characteristics achievable through the use of atomic layer deposition, it will be demonstrated that it has the potential to operate at temperature up to 398 K, and that power consumption is less than that of equivalent circuit in advanced CMOS technologies. In order to take advantage of both low power SETs and high CMOS drive efficiency, a hybrid 3D SET CMOS circuit is proposed.

Technology platform for the fabrication of titanium nanostructures

This paper presents two approaches for the fabrication of top-down titanium nanostructures. The first approach involves electron beam lithography followed by a tailored titanium plasma etching. The two main challenges of this process lie in the optimization of the negative tone Ma–N electroresist resolution and in the definition of a controlled titanium etching process for titanium patterns less than 20 nm thick and wide. The second proposed approach is a damascene process where the titanium nanostructures are buried in the oxide. Very shallow and narrow (20 nm × 20 nm) trenches are first patterned in the oxide and nanostructures are obtained by planarization of an evaporated titanium film. The dimensions of the structures are defined by the electron beam lithography resolution and the etching recipe. The third dimension is given by the titanium or any other metal thickness and can be controlled down to few nanometers thanks to the planarization step.

A Fabrication Process for Emerging Nanoelectronic Devices Based on Oxide Tunnel Junctions

We present a versatile nanodamascene process for the realization of low-power nanoelectronic devices with different oxide junctions. With this process we have fabricated metal/insulator/metal junctions, metallic single electron transistors, silicon tunnel field effect transistors, and planar resistive memories. These devices do exploit one or two nanometric-scale tunnel oxide junctions based on TiO2, SiO2, HfO2, Al2O3, or a combination of those. Because the nanodamascene technology involves processing temperatures lower than 300&#-80;C, this technology is fully compatible with CMOS back-end-of-line and is used for monolithic 3D integration.