Serge Maginot

Lessons in Language Design: Cost/Benefit Analysis of VHDL Features

This paper looks at the design of one successful hardware description language, VHSIC Hardware Description Language (VHDL) with a critical evaluation of particular language features. In the paper we identify features of VHDL that burden the language in terms of development time (i.e. price), performance of the implementation, and user-friendliness. We suggest a useful and instinctive tool to assess the redundancy of language features. We also give an explanation as to why such superfluous features are included in VHDL. While it is quite obvious that the restandardization process is not designed to remove features from VHDL, it is interesting, at the end of a major language redesign process, to draw lessons that can benefit language designers, implementors, and users.

Structuring the Environment

Digital integrated circuits compute binary information: in a stable state, each electrical node of a circuit may have one of two voltage values (OV or 5V in CMOS technologies) representing the two bit values 0 and 1. In hardware description languages, wires (signals) inside integrated circuits are thus usually (but not necessarily) modeled in a bit logic type.

Verilog and VHDL

Verilog is a hardware description language originally designed by Gateway for a proprietary simulation product. This company later merged with Cadence Design Systems, Inc. Since then, Verilog has been known and used as the language of the Cadence digital simulator.

Run-Time Checks

Warning: this chapter discusses dynamic checks that must be performed at run-time. This subject is very important for the safety and portability of VHDL models, but has very few practical implications for the designer, in the sense that it brings no new functionalities nor enforces a specific style. This chapter will mainly be of interest to implementors and support teams, rather than designers.

Mapping Expressions to Input Ports

VHDL’87 requires actual parts of port associations to be the reserved word open or to denote signals. In the case of an in port, the open association is allowed only if the corresponding formal in port declaration includes a default expression, in which case the port has a single driver with a constant value set to the default expression. That constant driver is used during simulation by the kernel to compute the effective value of the in port.

Inertial Signal Assignment Statement

VHDL’87 proposes two different models for signal propagation delay. The transport model corresponds to a pure propagation delay where an input waveform is propagated with no distortion: any pulse, however small, is transmitted. This mode is explicitly specified by appending the reserved word transport to the signal assignment symbol (<=).

Shift and Rotate Operators

VHDL’87 did not define any shift or rotate operators. The main problem here was reaching a consensus on a minimum set of operators. This has now been done, and VHDL’92 predefines four shift and two rotate operators.

Concurrent Signal Assignment

The two forms of signal assignment, conditional and selected, are very concise writings of powerful processes. Nevertheless, some aspects of their VHDL’87 syntax can be very confusing.

Predefined Attributes ’Behavior & ’Structure

The definitions of these two VHDL’87 attributes have been discussed extensively. The final conclusion was that if the definitions were not adapted, the attributes themselves would not correspond to a real need of the designer. In other words, nobody used these attributes.

Last-Delta Activation: Postponed Process

The concept of delta delay - simulation step seen as an infinitesimal delay - is the VHDL artifice to enforce causality in simulation. A time point of simulation consists in a variable number of delta delays that are necessary to the simulation semantics. It may happen that a designer wants to ignore what occurs during these delta delays in order to focus only on the “steady state” at the end of the time point, i.e., during the last delta.