Serge Pravossoudovitch

Design of routing-constrained low power scan chains

Scan-based architectures, though widely used in modern designs, are expensive in power consumption. Recently, we proposed a technique based on clustering and reordering of scan cells that allows to design low power scan chains according to Y. Bonhomme et al. (2003). The main feature of this technique is that power consumption during scan testing is minimized while constraints on scan routing are satisfied. In this paper, we propose a new version of this technique. The clustering process has been modified to allow a better distribution of scan cells in each cluster and hence lead to more important power reductions. Results are provided at the end of the paper to highlight this point and show that scan design constraints (length of scan connections, congestion problems) are still satisfied.

Yield Improvement, Fault-Tolerance to the Rescue?

With the technology entering the nano dimension, manufacturing processes are less and less reliable, thus drastically impacting the yield. A possible solution to alleviate this problem in the future could consist in using fault tolerant architectures to tolerate manufacturing defects. In this paper, we analyze the conditions that make the use of a classical triple modular redundancy (TMR) architecture interesting for a yield improvement purpose.

Un-Restored Destructive Write Faults Due to Resistive-Open Defects in the Write Driver of SRAMs

In this paper, we present an analysis of resistive-open defects in the write driver of SRAMs designed with the Infineon 65nm technology. From manufacturing data, we show that in some cases, a resistive-open defect may lead to a new type of dynamic behavior which has never been experienced in the past. This faulty behavior can be modeled as an un-restored destructive write fault (URDWF). Such URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier, and appears when a specific read operation is performed immediately after a specific write operation. Results of electrical simulations are presented to give a complete understanding of such a faulty behavior and to highlight the difference with a standard un-restored write fault (URWF) model. Next, a possible March test solution is presented to detect URDWF. Finally, a discussion is proposed on the opportunity to include new features in this part of the memory to easily distinguish between faults coming from the write driver (like URDWF) and those coming from other parts of the memory (sense amplifier, core-cells, etc.)

SoC Yield Improvement: Redundant Architectures to the Rescue?

Manufacturing processes in the nanoscale era are less and less reliable thus leading to lower and lower yield. In this paper we investigate the usage of TMR architectures for logic cores to increase SoC yield.

An SRAM Design-for-Diagnosis Solution Based on Write Driver Voltage Sensing

Diagnosis is becoming a major concern with the rapid development of semiconductor memories. It provides information about the location of manufacturing defects in the memory, and its effectiveness allows a fast yield ramp up. Most of existing diagnosis methods uses a fault dictionary to provide detailed information on fault localization. However, these solutions are most of the time unable to distinguish between all faults, and more importantly often fail to identify the actual faulty block of the memory. Identifying which block of a memory (core- cell array, write drivers, address decoders, pre-charge circuits, etc ...) is defective allows to saving considerable amount of time during the ramp up phase. In this paper, we propose a very low cost design-for- diagnosis (DfD) solution for identifying faulty write drivers. It consists in verifying logic and analog conditions that guarantee the fault-free behavior of the write driver. The proposed solution allows a fast diagnosis (only three consecutive write operations are needed to fully diagnose the write driver) and induces a low area overhead (about 0.5% for a 512 times 512 SRAM). Beside diagnosis, an additional interest of such a solution is its usefulness during a post-silicon characterization process, where it can be used to extract the main features of the write drivers (logic and analog levels on bit lines).

A Mixed Approach for Unified Logic Diagnosis

This paper presents a diagnosis methodology targeting most of the fault models used in practice today. This methodology is intended to be used to diagnose faulty behaviors in nanometric circuits for which the classical stuck-at fault model is far to cover all the realistic failures. The first phase of this methodology consists in the application of an Effect-Cause approach which relies on the two following main operations. The first one is based on critical path tracing (CPT) and consists in identifying lines in the Circuit Under Test (CUT) which can be the source of observed errors. The second one consists in allocating a set of possible fault models to each suspected line. In a second phase, we resort to a Cause-Effect approach applied on the set of suspects previously identified to prune the unlikely candidates and thus improve diagnosis resolution. The main advantage of this method is that it considers logical effects of the faults and does not need to handle each specific fault model explicitly during the diagnosis process. Experiments on ISCAS89 and ITC99 benchmark circuits show the efficiency of the proposed method in terms of diagnosis resolution.

Influence of Threshold Voltage Deviations on 90nm SRAM Core-Cell Behavior

Nanoscaled SRAMs are now becoming more and more prone to device parameter deviations. In this paper, we consider threshold voltage (Vt) deviations in 6T core-cells designed with 90 nm technology. Static faults (transition and read destructive) but also dynamic faults (dynamic read destructive) are obtained as resulting faulty behaviors. Moreover, electrical data show that PVT (process, voltage, temperature) corners that maximize the detection of these faults are quite unconventional. Especially, we show that Vt deviations have their main impact at low voltage while hard defects, such as resistive-open defects in the core-cell, better manifest themselves at high voltage. This study of parameter deviations opens an additional problematic for the test of nanoscaled SRAMS that will be much more severe in deeper technologies (65 nm and 45 nm).