Arnaud Virazel

Resistive-open defect influence in SRAM pre-charge circuits: analysis and characterization

In this paper, we present an exhaustive study on the effects of resistive-open defects in the pre-charge circuits of SRAM memories. In particular, we have analyzed the influence of resistive-opens placed in different locations of these circuits. In SRAM memories, the pre-charge circuits operate the pre-charge and equalization at a certain voltage level, in general Vdd, of all the couples of bit lines of the memory array. This action is essential in order to ensure correct read operations. Each defect studied in this paper disturbs the pre-charge circuit in a different way and for different resistive ranges, but the produced effect on the normal memory action is always the perturbation of the read operations. This faulty behavior can be modeled with un-restored write faults (URWFs) and un-restored read faults (URRFs), because there is an incorrect pre-charge/equalization of the bit lines after a write or read operation that disturbs the following read operation. In the last part of the paper, we demonstrate that the test of URWFs is more rentable in terms of resistive defect detection than that of URRFs.

Power-Aware Test Data Compression for Embedded IP Cores

Scan architectures, though widely used in modern designs for testing purpose, are expensive in test data volume and power consumption. To solve these problems, the authors propose in this paper to modify an existing test data compression technique so that it can simultaneously address test data volume and power consumption reduction for scan testing of embedded intellectual property (IP) cores. Compared to the initial solution that fill dont-care bits with the aim of reducing only test data volume, here the assignment is performed to minimize also the power consumption. The proposed power-aware test data compression technique is applied to the ISCAS89 and ITC99 benchmark circuits and on a number of industrial circuits. Results show that up to 20times reduction in test data volume and 95% test power reduction can be obtained simultaneously

Resistive-Open Defects in Core-Cells

In this chapter, an exhaustive analysis of the impact of resistive-open defects in core-cells of SRAMs is presented with particular emphasis on dynamic faults. Resistive-open defects appear frequently in VDSM technologies and induce a modification of the timing within the memory (delay faults). Among the faults induced by such resistive-open defects, there are static and dynamic Read Destructive Faults (RDFs), Deceptive Read Destructive Faults (DRDFs), Incorrect Read Faults (IRFs), Transition Faults (TFs), and static and dynamic Data Retention Faults (DRFs). Each of them requires specific test conditions, and several March tests are needed to cover all these faults. The first part of the chapter presents an electrical analysis and characterization of the core-cell, with the identification of fault models related to resistive-open defects in the core-cell. In the following, the state of the art of March procedures for the test of all core-cell dynamic faults is presented. The last section of the chapter discusses the impact of technology scaling on the failures induced by resistive-open defects in the core-cells.

Resistive-Open Defects in Address Decoders

This chapter targets the study of dynamic faults that affect the address decoders of SRAMs, in particular ADOFs (Address Decoder Open Faults) and resistive-ADOFs that are caused by intra-gate pure open and resistive-open defects. Experiments show that resistive-ADOFs, which are a generalization of ADOFs, require more stringent timing constraints for their sensitization. Several algorithmic solutions are effective to test these faults. These so-lutions are mainly based on the ‘Sachdev’s pattern.’ One of these test solutions consists in a compact 2 N March test that can be em-bedded in existing March tests, without modifying their complexity and their capability to cover the former target faults. A meaningful example of a modified test algorithm covering ADOFs is March iC-, which is an improved version of March C-.

Faults Due to Process Variations in SRAMs

This chapter studies the impact of process variations and parasitic phenomena on SRAM operation. In particular, fault modeling and test solutions are detailed. The first section focuses on threshold voltage deviations within the SRAM core-cell that lead to static and dynamic faults, such as TF and dRDF. Next, it is shown that leakage currents flowing through the pass gates of unselected core-cells may influence the read operation causing leakage read faults (LRFs). The last section of the chapter presents the Complex Read Fault (CRF) that models the cumulative effect of multiple electric phenomena in several SRAM sub-circuits, which contribute to reduce the success of the read operation.

Basics on SRAM Testing

This chapter presents the context of this book. After an introduction offering an overview of the different types of memories, it focuses on SRAMs. The main aspects of SRAM testing are then tackled, and the two main classes of faults affecting SRAMs, i.e., static and dynamic faults, are presented. After that, the standard notation of a March test is described. This category of memory test is commonly used due to the low complexity of the algorithms. Moreover, their flexibility allows reaching a high coverage level for many fault models. In the last part of this chapter, the main methods targeting automatic generation of March tests and memory fault simulation are discussed.

Resistive-Open Defects in Sense Amplifiers

This chapter presents an exhaustive analysis of resistive-open defects in the sense amplifiers of SRAMs. It shows that some resistive-open defects may lead to faulty behaviors that can be modeled by dynamic two-cell Incorrect Read Faults of two different types (d2cIRF1 and d2cIRF2). Such fault models represent failures in a sense amplifier that prevent it to perform any read operations (in case of d2cIRF1) or only a single type of read operation (either r0 or r1 in case of d2cIRF2). Results of electrical simulations, performed with a 65-nm SRAM technology, are reported to provide a complete understanding of such a faulty behavior. Finally, possible March test solutions are proposed to detect all d2cIRFs (type 1 and type 2) in SRAM sense amplifiers.

Resistive-Open Defects in Write Drivers

This chapter presents an analysis of resistive-open defects in the write drivers of SRAMs. It shows that resistive-open defects may lead to dynamic behaviors. These faulty behaviors can be modeled as Slow Write Driver Faults (SWDFs) and Un-Restored Destructive Write Faults (URDWFs). A SWDF involves an erroneous write operation when the same write driver performs two successive write operations with opposite data values. An URDWF is a consequence of the structural dependencies that exist between the write driver and the sense amplifier and appears when a specific read operation is performed immediately after a specific write operation. Electrical simulations, performed with a 65-nm technology, are reported to give a complete understanding of such faulty behaviors. Finally, possible March test solutions are proposed to detect all SWDFs and URDWFs.

Diagnosis and Design-for-Diagnosis

Nowadays, the latest technologies permit very high degree of integration allowing a number of circuits per die much higher than in the past. These new technologies are also more prone to defects, parasitic phenomena, and manufacturing variations, which may drastically reduce the yield. For this reason, fault detection, diagnosis, and defect localization are used in order to repair defective memories thus improving SoC reliability and yield. This chapter focuses on diagnosis and design-for-diagnosis techniques dedicated to SRAMs.

Resistive-Open Defects in Pre-charge Circuits

In SRAMs, the pre-charge circuits operate the pre-charge and equalization at a fixed voltage level (in general VDD) of all couples of bit lines in the memory array. This action is essential to ensure correct read operations. This chapter presents the study of the effects of resistive-open defects in the pre-charge circuits of SRAMs. Each defect produces a perturbation of the read operation, with an incidence that depends on the location and the resistance value. The malfunction of the pre-charge circuit leads to two types of dynamic faults named Un-Restored Write Faults (URWFs) and Un-Restored Read Faults (URRFs). These faults are mainly due to an incomplete pre-charge/equalization of the bit lines after a write or read operation that disturb the following read operation. Experimental results show that the test of URWFs is more effective than that of URRFs, as well as that ‘at-speed test’ is a requirement for effective fault coverage. In the second part of the chapter, the state of the art of URWF test algorithms is presented.