Setareh Rafatirad

Event composition operators: ECO

Events are at least as important as objects in modeling the dynamic universe. Modeling the real world and weaving the web of events require Composite Events that are valid constitution of atomic and composite sub-events. The progress in event composition has been limited to construction of some entities and relationships in upper ontologies such as Event-Model-F, and DSO ontology that are extensions of BFO,DOLCE, and E-Model. For building a composite event from atomic events, different operators must be used to provide right attributes for this event. Event Composition Operators on all attributes of events should be defined. The knowledge of context semantics of sub-event facets should be used for valid population of the resulting composite event attributes. Our contribution and focus in this paper is to define and implement such event composition operators on spatial and temporal aspect of events.

A comprehensive study of visual event computing

This paper contains a survey on aspects of visual event computing. We start by presenting events and their classifications, and continue with discussing the problem of capturing events in terms of photographs, videos, etc, as well as the methodologies for event storing and retrieving. Later, we review an extensive set of papers taken from well-known conferences and journals in multiple disciplines. We analyze events, and summarize the procedure of visual event actions. We introduce each component of a visual event computing system, and its computational aspects, we discuss the progress of each component and review its overall status. Finally, we suggest future research trends in event computing and hope to introduce a comprehensive profile of visual event computing to readers.

Functional units power gating in SMT processors

Power consumption has emerged as a primary concern in processor design constraints. Power-aware techniques are being applied at all levels of circuit and system design. These techniques aim at reducing power or energy dissipation in all types of computer equipments while meeting a desired throughput. At the architectural level, power-aware design has been an active area of research in the last decade for superscalar processors. Simultaneous multithreading processor (SMT), introduced as a complementary architecture to superscalar to increase throughput, has received less attention in the context of low-power design techniques. In SMT processors functional units are one of the major power consumers. In this paper we first study the opportunity for reducing the power consumption of functional units. Our results show that functional units are idle for a significant portion of the total execution cycle. Then we reuse and evaluate a microarchitectural technique to reduce functional unit power through power gating which has been recently proposed for superscalar processors. We show that in SMT processors, this technique can reduce floating point unit power considerably while maintaining performance.

Big biomedical image processing hardware acceleration: A case study for K-means and image filtering

Most hospitals today are dealing with the big data problem, as they generate and store petabytes of patient records most of which in form of medical imaging, such as pathological images, CT scans and X-rays in their datacenters. Analyzing such large amounts of biomedical imaging data to enable discovery and guide physicians in personalized care is becoming an important focus of data mining and machine learning algorithms developed for biomedical Informatics (BMI). Algorithms that are developed for BMI heavily rely on complex and computationally intensive machine learning and data mining methods to learn from large data. The high processing demand of big biomedical imaging data has given rise to their implementation in high-end server platforms running software ecosystems that are optimized for dealing with large amount of data including Apache Hadoop and Apache Spark. However, efficient processing of such large amount of imaging data running computational intensive learning methods is becoming a challenging problem using state-of-the-art high performance computing server architectures. To address this challenge, in this paper, we introduce a scalable and efficient hardware acceleration method using low cost commodity FPGAs that is interfaced with a server architecture through a high speed interface. In this work we present a full end-to-end implementation of big data image processing and machine learning applications in a heterogeneous CPU+FPGA architecture. We develop the MapReduce implementation of K-means and Laplacian Filtering in Hadoop Streaming environment that allows developing mapper functions in non-Java based languages suited for interfacing with FPGA-based hardware accelerating environment. We accelerate the mapper functions through hardware+software (HW+SW) co-design. We do a full implementation of the HW+SW mappers on the Zynq FPGA platform. The results show promising kernel speedup of up to 27× for large image data sets. This translate to 7.8× and 1.8× speedup in an end-to-end Hadoop MapReduce implementation of K-mean s and Laplacian Filtering algorithm, respectively.

Contextual Augmentation of Ontology for Recognizing Sub-events

With the advances in technology and proliferation of cheap storage, high rate of digital multimedia interaction signifies the increasing need of computer users for a decent application to organize personal media in a meaningful way. In this paper, we want to organize personal media in terms of the sub-events they cover. A semantic gap exists between media, and peoples perception of the events and memories associated with this media. A framework is needed to address such gap. This paper describes a novel model-based approach for partitioning and organizing personal photo archive in terms of high-level subevents that capture and represent human experience. Since photos are the most ubiquitous and prolific form of user generated content, we focus on the automatic annotation of personal photo collection in this paper. We introduce ROntology (Recognition-Ontology) that is a context-aware model with concrete contextual information for subevent recognition. Currently our approach utilizes the mereological, spatial and temporal properties of modeled-events in R-Ontology. Personal media will then populate R-Ontology. We tested this approach using our personal photo archive describing two different scenarios: Trip and Indianwedding.

MEDIALIFE: from images to a life chronicle

Amarnath Gupta Univ. of California Irvine 9500 Gilman Drive La Jolla, CA 92093, USA gupta@sdsc.edu Setareh Rafatirad Dept. of Computer Science Univ. of California Irvine Irvine, USA, CA 92697 srafatirad@gmail.com Mingyan Gao Dept. of Computer Science Univ. of California Irvine Irvine, USA, CA 92697 gaomingyan@gmail.com Ramesh Jain Dept. of Computer Science Univ. of California Irvine Irvine, USA, CA 92697 jain@ics.uci.edu

Thread scheduling based on low-quality instruction prediction for simultaneous multithreaded processors

A simultaneous multithreaded (SMT) processor is capable of executing instructions from multiple threads in the same cycle. SMT in fact was introduced as a complementary architecture to superscalar to increase the throughput of the processor. Recently, several computer manufacturers have introduced their first generation SMT architecture. SMT permits multiple threads to compete simultaneously for shared resources. An example is the race for the fetch unit which is a critical logic responsible for thread scheduling decisions. When more threads than hardware execution contexts are available, the decision of choosing the best threads to fetch instructions from, will affect the processors efficiency. In this paper the authors presented a new approach to choose the most useful threads among all available threads while they compete on a shared resource. The quality of instructions was identified based on the time they spend in the instruction queue. Low-quality instructions spend more time in the instruction queue. Accordingly threads with fewer number of low-quality instructions have a higher contribution to the entire processor throughput. In an experimental study, such low-quality instructions in each thread was identified to a maximum of 92% accuracy (average 72%). The authors exploited this to increase the overall processor throughput by giving higher priority to threads with lesser number of low-quality instructions. Overall an average of 11% performance improvement was achieved over the traditional algorithm that schedules threads in a round-robin fashion.

Ensemble learning for effective run-time hardware-based malware detection: a comprehensive analysis and classification

Malware detection at the hardware level has emerged recently as a promising solution to improve the security of computing systems. Hardware-based malware detectors take advantage of Machine Learning (ML) classifiers to detect pattern of malicious applications at run-time. These ML classifiers are trained using low-level features such as processor Hardware Performance Counters (HPCs) data which are captured at run-time to appropriately represent the application behaviour. Recent studies show the potential of standard ML-based classifiers for detecting malware using analysis of large number of microarchitectural events, more than the very limited number of HPC registers available in today’s microprocessors which varies from 2 to 8. This results in executing the application more than once to collect the required data, which in turn makes the solution less practical for effective run-time malware detection. Our results show a clear trade-off between the performance of standard ML classifiers and the number and diversity of HPCs available in modern microprocessors. This paper proposes a machine learning-based solution to break this trade-off to realize effective run-time detection of malware. We propose ensemble learning techniques to improve the performance of the hardware-based malware detectors despite using a very small number of microarchitectural events that are captured at run-time by existing HPCs, eliminating the need to run an application several times. For this purpose, eight robust machine learning models and two well-known ensemble learning classifiers applied on all studied ML models (sixteen in total) are implemented for malware detection and precisely compared and characterized in terms of detection accuracy, robustness, performance (accuracy × robustness), and hardware overheads. The experimental results show that the proposed ensemble learning-based malware detection with just 2 HPCs using ensemble technique outperforms standard classifiers with 8 HPCs by up to 17%. In addition, it can match the robustness and performance of standard ML-based detectors with 16 HPCs while using only 4 HPCs allowing effective run-time detection of malware.

Comprehensive assessment of run-time hardware-supported malware detection using general and ensemble learning

Recent studies have demonstrated the effectiveness of Hardware Performance Counters (HPCs) for detecting pattern of malicious applications. Hardware-supported detectors utilize Machine Learning (ML) classifiers for malware detection by analyzing a large number of HPC features, more than the very limited number of HPC registers available in modern microprocessors. Obtaining more HPCs requires running the application (malware or benign) more than once to collect the required data, which in turn makes the solution less practical for run-time detection of malware. In response to this challenge, in this work, we first identify the critical HPC features required for malware detection. Next, we explore the use of various ML techniques to classify benign and malware applications using the selected HPCs at run-time. Further, we investigate the effectiveness of ensemble learning in improving the performance of ML classifiers. For this purpose, we apply AdaBoost on all general ML classifiers. We thoroughly compare the general and ensemble ML classifiers in terms of accuracy, robustness, performance, and hardware overhead. The experimental results indicate that ensemble learning enhances the performance of malware detection for rule-based and tree-based algorithms up to 13%. However, it diminishes the performance of neural network and Bayesian network-based detectors by 6% and 4%, respectively.

Context-Based Event Ontology Extension in Multimedia Applications

An approach focused on inferring the finest possible sub event witnessed by individual photographs in a personal photo stream of an event is presented in this work using image metadata (timestamp, location, and camera parameters), information about the user, ontological event model, mobile device connectivity, web services, and external data sources. We introduce Event Ontology Augmentation that is a new technique to obtain, refine, and validate expressive event tags in the context of personal photo annotation. In this technique, an ontological event model is used to describe the vocabulary for a general domain event such as trip. The event-ontology is extended with context-information from heterogeneous data sources. We introduce plausibility measure for ranking and selecting the best possible sub event category related to a group of photos in a photo stream.