Seung-bin You

A 101-dB SNR hybrid delta-sigma audio ADC using post integration time control

A 3rd-order hybrid (continuous-time and discrete-time) delta-sigma audio ADC, implemented in 65 nm CMOS process, dissipates 15 mW and occupies an active die area of 0.28 mm2. A post integration time control (PITC) technique is proposed for calibration of the RC time constant variation of the continuous-time integrator. In addition, a jitter insensitive pulse generator (JIPG) circuit overcomes the degradation of SNR due to the feedback DAC clock jitter. The measured SNR and DR are 101 dB and THD is -94 dB.

A 1.3-mW per-channel 103-dB SNR stereo audio DAC with class-D head-phones amplifier in 65nm CMOS

The stereo audio DAC with novel single-ended class-D amplifier achieving a 103-dB SNR is fully integrated in a 65 nm CMOS technology. Novel asymmetric pulse-width modulation (PWM) is applied to minimize switching noise and nonlinearity in the class-D amplifier. The adjustable delta-sigma modulator is also used to suppress supply-voltage modulation. All the functions needed for portable audio playback are implemented in a 0.53-mm2 area dissipating only 1.3-mW per channel from a 2.5-V supply.

A 4mW per-Channel 101dB-DR Stereo Audio DAC with Transformed Quantization Structure

A 2.7V 4mW per-channel 20-bit 48kS/s sigma-delta stereo audio DAC, integrated in a 0.13mum CMOS technology, achieves a dynamic range (DR) of 101dB and occupies an active die area of 0.82mm2. The transformed quantization technique is proposed to decrease tonal behavior generated in low order sigma-delta modulator and the circuit is implemented to operate with optimal current consumption. The measured SNR and peak SNDR are 102dB and 95dB, respectively

A 1.1 V 82.3dB audio ΔΣ ADC using asynchronous SAR type quantizer

A switched-capacitor second-order audio ΔΣ analog-to-digital converter (ADC) is presented. The proposed ΔΣ ADC employs low-distortion input feed-forward architecture to relax the linearity requirement of the integrators. A 4-bit asynchronous successive approximation register (SAR) type internal quantizer is used for power efficient design by incorporating the analog adder with the quantizer. A tree-structured dynamic element matching (DEM) technique is employed to reduce the distortion resulted from the capacitor mismatch in the feedback digital-to-analog converter (DAC). The prototype ΔΣ ADC implemented in a 45nm CMOS process achieves 85.4 dB peak signal-to-noise ratio (SNR), 82.3 dB peak signal-to-noise and distortion ratio (SNDR) and 98.1 dB dynamic range (DR) for a signal bandwidth of 24 kHz while consuming 517.4 μW at 1.1 V supply voltage.

A self-calibration 103-dB SNR stereo audio DAC with true-GND class-D headphone drivers in 45nm CMOS

A stereo audio DAC with ground-centered class-D headphone drivers is fully integrated in a 45nm CMOS technology. A built-in self-calibration is proposed to minimize DC offset voltage causing static power dissipation. The asymmetric averaging PWM is also applied to improve linearity and suppress switching noise and loss. The measured SNR and DR are 103dB and 98dB, respectively.

A calibration-free 3V 16b 500kS/s 6mW 0.5mm/sup 2/ ADC with 0.13 /spl mu/m CMOS

A calibration-free 3V 6mW 16-bit 500kS/s cyclic ADC with an active die area of 0.5mm/sup 2/ is implemented in a 0.13 /spl mu/m CMOS. The proposed converter adopts a 2.5-bit/stage cyclic architecture and capacitor layout scheme to achieve improved matching accuracy, the DNL and INL of /spl plusmn/0.90 LSB and /spl plusmn/6.1 LSB, respectively.

A calibration-free 3.0 V 12-bit 20 MSPS A/D converter

A calibration-free 3 V 12-bit 20 MSPS pipelined analog-to-digital (A/D) converter was implemented using 0.35 /spl mu/m CMOS technology. The proposed hybrid capacitor switching technique of two feedback capacitors is applied to improve the linearity which is limited by component mismatch depending on the process. Since the proposed technique can be implemented by simple circuits compared with previous self-calibration techniques, it allows smaller area and lower power consumption and it is applicable to general pipelined architectures. Other technique proposed to improve the linearity is a capacitor array layout scheme which is insensitive to the parasitic effect of capacitor top plates. The A/D converter occupies a die area of 2.57 mm/sup 2/ (1260 /spl mu/m/spl times/2040 /spl mu/m) excluding pad ring and dissipates 135 mW at a 20 MHz clock rate with a 3 V single supply. Typical differential nonlinearity (DNL) and integral nonlinearity (INL) are /spl plusmn/0.72 LSB and/spl plusmn/1.22 LSB, respectively.