Seung-jae Jung

A non-linear ReRAM cell with sub-1μA ultralow operating current for high density vertical resistive memory (VRRAM)

A non-linear RRAM cell with sub-1μA ultralow operating current has been successfully fabricated for high density vertical ReRAM (VRRAM) applications. A uniform and reproducible low power resistive switching was achieved by engineering transition metal oxides and imposing thin insulating layer as a tunnel barrier. The non-linear I-V characteristics ensure the possible incorporation of RRAM cell into high density cross-type array structure including VRRAM. By varying the current compliance, a multi level switching behavior was obtained. Moreover, excellent endurance of more than 107 cycles without read disturbance for up to 104 seconds was demonstrated.

Five-Step (Pad–Pad Short–Pad Open–Short–Open) De-Embedding Method and Its Verification

We present the method for five-step (pad-pad short-pad open-short-open) on-chip parasitic de-embedding. Its validation is verified by gate electrode resistance and input capacitance of transistors based on 45 -nm CMOS process. Optimized dummy structures to remove the parasitic components due to the pad and routing metal are proposed. Parameters extracted by the proposed method have excellent physical and theoretical trends.

Scalable Model of Substrate Resistance Components in RF MOSFETs With Bar-Type Body Contact Considered Layout Dimensions

Scalable model of substrate resistance components for radio-frequency MOSFETs fabricated by 65-nm CMOS technology with the bar-type body contact set in a horizontal direction to gate poly is presented. We consider various layout dimensions, such as channel length; unit finger width; number of fingers; distance between body contact and active region; and gate poly to gate poly distance on substrate resistance modeling. By using our model, the output admittance of the MOSFETs is well matched up to 50 GHz. The proposed models for substrate resistance are more accurate for devices with various geometries than previous substrate resistance models.

Influence of surface properties on the performance of Cu(In,Ga)(Se,S)2 thin-film solar cells using Kelvin probe force microscopy

We have investigated the sulfurization process in a Cu(In,Ga)(Se,S)2 (CIGSS) absorber layer fabricated by a two-step sputter and selenization/sulfurization method in order to make an ideal double-graded band-gap profile and increase the open circuit voltage (Voc). The sulfurization process was controlled by temperature from 570 °C to 590 °C without changing H2S gas concentration and reaction time. Although the energy band-gap of the CIGSS absorber layer was increased with increasing sulfurization temperature, the Voc of the completed CIGSS device fabricated at 590 °C sulfurization temperature did not increase. In order to investigate this abnormal Voc behavior, the CIGSS absorber layer was measured by local electrical characterization utilizing Kelvin probe force microscopy, especially in terms of grain boundary potential and surface work function. Consequently, the abnormal Voc behavior was attributed to the degradation of grain boundary passivation by the strong sulfurization process. The optimum sulfurization temperature plays an important role in enhancement of grain boundary passivation. It was also verified that the Voc degradation in the CIGSS solar cell fabricated by the two-step method is more influenced by the grain boundary passivation quality in comparison with the slight non-uniformity of material composition among grains.

RF Model of BEOL Vertical Natural Capacitor (VNCAP) Fabricated by 45-nm RF CMOS Technology and Its Verification

A radio-frequency equivalent circuit model for the symmetric vertical natural capacitor (VNCAP) in a 45 nm low-standby-power CMOS process is presented. The average effective capacitance density of 2.24 fF/ mum2 is obtained from VNCAPs of 1 times (M1 - M5) + 2 times (M6 - M7) metal-layer configuration after the open-short de-embedding procedure. The proposed model consists of main series capacitance network and lossy substrate network. The accuracy of the VNCAP model is verified S-parameters, effective capacitance Ceff, and quality factor (Q) up to 15 GHz. The proposed model can accurately describe the frequency characteristics of S-parameters, Ceff, and Q-factor up to 15 GHz for VNCAPs with different widths and lengths.

Effect of technology scaling on RF performance of the transistors fabricated by standard CMOS technology

Cut-off frequency (f_T) of 300 GHz and 230 GHz for NMOS and PMOS is demonstrated for transistors with a gate length of 35 nm fabricated by 45 nm standard CMOS technology. Current gain (H₂₁) and noise (flicker and thermal) is improved with scaling down technology. Power gain (G_u) increase is slow down and even saturated at 45 nm as technology advances. Such saturation in power gain is attributed to rapid increase in g_ds (drain conductance). Additional efforts are required to reduce g_ds for continuous improvement in power gain with the scaling. V_th optimization can be one of options to achieve better g_ds.

Highly reliable ReRAM technology with encapsulation process for 20nm and beyond

ReRAM cell performance and reliability have been improved through process optimization. Encapsulated ReRAM cell with SiN capping layer shows excellent endurance, read disturb, and retention characteristics. We demonstrated that effective oxygen barrier encapsulation is critical for keeping ReRAM performance in an aggressively scaled technology node.