Seung Jin Yeom

Platinum(100) hillock growth in a Pt/Ti electrode stack for ferroelectric random access memory

The Pt hillock in a Pt/Ti electrode stack has been the main concern in ferroelectric random access memory due to the reliability problem. The origin of the hillock formation is the compressive stress, and the main mass transport mechanism for hillock formation is the grain boundary diffusion for thin films with a columnar structure. However, the hillock growth orientation and mechanism have not been reported. In this study, we found that an orientation relationship of Pt(100)hillock//Pt(111)thin film existed between the Pt hillock and the thin film. The Pt hillock was a single crystal having facets with polyatomic steps. From these results, we suggest that the Pt hillock growth mechanism is the layer growth of flat faces, which shapes the hillock into a tetrahedron single crystal.

Platinum Hillocks in Pt/Ti Film Stacks Deposited on Thermally Oxidized Si Substrate

The stress dependence of platinum hillock formation during post thermal cycling was investigated in Pt/Ti electrode stacks. Annealing temperatures were varied from room temperature (RT) to 650°C. High compressive stress was generated during electrode annealing by the Ti diffusion into the platinum layer followed by oxidation in the platinum grain boundaries. The compressive stress was the major driving force for the hillock formation on the platinum surface. Thus, the Ti glue layer was oxidized before platinum deposition to reduce the Ti diffusion. The Pt/TiOx electrode stack retained its smooth platinum surface after the electrode annealing of 650°C for 30 min in O2. The Pt/TiOx interface remained flat even after the ferroelectric annealing at 800°C, which was performed after SrBi2Ta2O9 (SBT) deposition. Moreover, the remanent polarization (2Pr) of the SBT capacitor was increased to 17 µC/cm2 on the Pt/TiOx electrode stack, up from 13 µC/cm2, which was the value on the Pt/Ti electrode stack.

Electrical properties of Bi4-xLaxTi3O12 ferroelectric thin films prepared by metalorganic decomposition method

Bi4-xLaxTi3O12 (BLT) ferroelectric thin films were prepared on a Pt/TiOx/SiO2/Si substrate using metalorganic decomposition (MOD) method, and their electrical properties were evaluated with thickness, composition and crystallization annealing temperature. Irrespective of the preparation conditions, BLT films were c-axis oriented, and had a dense surface morphology without pore to produce smooth Pt/BLT/Pt interfaces of capacitor. The film thickness was controlled as 90 nm to obtain a low coercive voltage (2Vc) without the problem of capacitor short-fail. The proper composition of Bi3.35La0.85Ti3O12 was selected for the largest switching polarization (P*-P∧), good fatigue endurance and a low leakage current density (JL). After crystallization annealing at 700°C, the optimized film of 90 nm Bi3.35La0.85Ti3O12 showed the good electrical properties, such as 2Vc of 2.0 V, P*-P∧ of 13 µC/cm2, JL of 1×10-6 A/cm2 at a applied voltage of 3 V and no polarization loss up to 1×1011 fatigue cycles, for ferroelectric random access memory (FeRAM) application.

Thickness Effects on Physical and Ferroelectric Properties of Bi3.35La0.85Ti3O12 (BLT) Films with c-axis-Preferred and Random Orientations

Thickness effects on dependences of physical and ferroelectric properties were investigated for two kinds of Bi3.35La0.85Ti3O12 (BLT) film with c-axis-preferred and random orientations. BLT films were prepared on Pt/TiOx/SiO2/Si substrates by the metalorganic decomposition (MOD) method, and their crystalline orientation was controlled by baking and rapid thermal annealing (RTA) conditions. When scaling down thickness from 210 to 70 nm, the c-axis-oriented film showed a big reduction in switching polarization (P*-P∧) from 13 to 6 µC/cm2 due to the predominant negative effect of the increased degree in c-axis-preferred orientation rather than the positive effect of increased grain size. However, the randomly oriented film showed no physical change such that it maintained a large polarization of 15–16 µC/cm2 in spite of the thickness reduction. Coercive field (2Ec) and fatigue-free property showed no significant thickness dependence for both BLT films.

Intrinsic stress dependence of Pt hillock formation and its related electrical properties of SBT capacitor

Abstract The Pt/Ti electrode stacks were deposited on the SiOx/Si substrate by DC magnetron sputtering. The Pt layers were deposited at various temperature of RT∼500°C. These electrode stacks were annealed at 650°C for 30min in O2ambient. A lot of high hillocks were observed on the Pt surface deposited at low temperatures (RT∼300°C) after the anneal process. But the hillocks were decreased in both number and height with increasing the deposition temperature of the Pt layer. We found in both SEM inspection and stress measurement that the deposition temperature dependence of the Pt hillock formation could be explained by the difference in the intrinsic stress generated during deposition process. We also demonstrated the effect of Pt hillocks on electrical properties of SBT capacitor. The 2Pr values of the SBT capacitors were about 13μ C/cm2regardless of the Pt deposition temperatures. But the short probabilities were decreased with the increase of the Pt deposition temperatures. This result is well consiste...

Effects of Crystallization Annealing Sequence for SrBi2Ta2O9 (SBT) Film on Pt/SBT Interface Morphology and Electrical Properties of Ferroelectric Capacitor

SrBi2Ta2O9 (SBT) film was crystallized to form fine grains and a smooth surface by rapid thermal annealing (RTA), but form large grains and a rough surface by main furnace annealing. The sequence of furnace annealing was changed to improve the morphology of the Pt/SBT interface and the leakage property of a Pt/SBT/Pt capacitor. For the conventional sequence of furnace annealing before top electrode deposition, the capacitor showed a good switching polarization (P*-P∧) of 17 µC/cm2 but a high short fail rate of 56% due to the rough Pt/SBT interface. However, using the new sequence of furnace annealing after top electrode deposition on RTA-treated SBT film, a very smooth Pt/SBT interface and a resultant low short fail rate of 7% was obtained, but the value of P*-P∧ was decreased to 14 µC/cm2 due to a restrained grain growth of the SBT film under Pt top electrode.

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

A 16 Mb 1TIC FeRAM with a novel cell structure has been successfully developed with 0.25 /spl mu/m process technology using (Bi,La)/sub 4/Ti/sub 3/O/sub 12/ (BLT) capacitors for the first time. The developed FeRAM is highly scalable and reliable as a result of applying an MTP (merged top electrode and plate line) structure and BLT stacked capacitor, respectively.

(Bi, La)4Ti3O12 (BLT) thin films grown from nanocrystalline perovskite nuclei for ferroelectric memory devices

Using nanocrystalline perovskite nuclei, (117) oriented-(Bi,La)4Ti3O12(BLT) thin films were grown using a noble bake process for nonvolatile ferroelectric memory devices. The c-axis oriented BLT thin films have a remanent polarization (2Pr) of 8.0μC∕cm2 at a 3V driving voltage, and the (117) oriented films have a 2Pr value of about 25μC∕cm2. The BLT capacitors, grown on a platinum electrode via nanocrystalline perovskite nuclei, had fatigue and imprint free characteristics after applying 1×1011 switching cycles and for ten years at a 125°C stress. The average sensing margin of the (117) oriented BLT thin films was approximately 700mV for a 0.65μm2 cell size and a sufficient signal margin for ten years was indicated, based on the extrapolation of the measured data for high density ferreoelectric random access memory applications.

Ferroelectric Memories using Randomly Oriented (Bi1-xLax)4Ti3O12 Films

We report on superior reliabilities at high temperature of ferroelectric memories using [Bi1-xLax]4Ti3O12 (BLT) films, which are randomly oriented by special bake treatments. The ferroelectric memories are based on 0.35 µm complementary metal–oxide–semiconductor (CMOS) technology ensuring ten-year retention and imprint at 175°C. This excellent reliability resulted from newly developed BLT ferroelectric films with superior reliability performance at high temperatures, and also resulted from robust integration schemes free from ferroelectric degradation due to process impurities such as moisture and hydrogen.

Ohmic Contact Properties of Tungsten Plug and Ferroelectric Properties of (Bi,La)4Ti3O12 Thin Film in Stacked Capacitor Structure.

A stacked Bi3.35La0.85Ti3O12 (BLT) capacitor with Pt/IrOx/Ir bottom electrode stack was successfully integrated on a tungsten (W) plug up to metallization for mega-bit ferroelectric random access memory. The optimized BLT film was prepared using the metal-organic decomposition method and the total thermal budget during the integration was 2 h at 650°C in oxygen ambient. For ensuring the thermal stability of the plug, the buried barrier structure was fabricated with both W recess and chemical-mechanical polishing of the TiN barrier layer. The robust W plug showed good ohmic contact behavior and the contact resistance was about 200 Ω/plug after metallization at the contact size of 0.30 µm. The electrical properties of the BLT capacitor were also evaluated via the plug after metallization. The remanent polarization (2Pr) was about 26 µC/cm2 and the leakage current density was about 3 ×10-7 A/cm2 at the applied voltage of 3 V. Fatigue loss after 1 ×1011 cycles was about 3% at the switching voltage of 3 V.