Nam-Kyeong Kim

Noble FeRAM technologies with MTP cell structure and BLT ferroelectric capacitors

A 16 Mb 1TIC FeRAM with a novel cell structure has been successfully developed with 0.25 /spl mu/m process technology using (Bi,La)/sub 4/Ti/sub 3/O/sub 12/ (BLT) capacitors for the first time. The developed FeRAM is highly scalable and reliable as a result of applying an MTP (merged top electrode and plate line) structure and BLT stacked capacitor, respectively.

(Bi, La)4Ti3O12 (BLT) thin films grown from nanocrystalline perovskite nuclei for ferroelectric memory devices

Using nanocrystalline perovskite nuclei, (117) oriented-(Bi,La)4Ti3O12(BLT) thin films were grown using a noble bake process for nonvolatile ferroelectric memory devices. The c-axis oriented BLT thin films have a remanent polarization (2Pr) of 8.0μC∕cm2 at a 3V driving voltage, and the (117) oriented films have a 2Pr value of about 25μC∕cm2. The BLT capacitors, grown on a platinum electrode via nanocrystalline perovskite nuclei, had fatigue and imprint free characteristics after applying 1×1011 switching cycles and for ten years at a 125°C stress. The average sensing margin of the (117) oriented BLT thin films was approximately 700mV for a 0.65μm2 cell size and a sufficient signal margin for ten years was indicated, based on the extrapolation of the measured data for high density ferreoelectric random access memory applications.

19.2 A 93.4mm 2 64Gb MLC NAND-flash memory with 16nm CMOS technology

This paper presents a 64Gb MLC NAND-Flash memory fabricated with 16nm CMOS process technology to achieve high density and as small as 93.4mm2 die area. The chip consists of two planes of 1072 blocks each. A block consists of a string with 128 cells and a page size with 16KB and spare area for error-correction coding (ECC), totaling 4MB of capacity. The chip supports negative-level wordline drivability to increase cell Vth margin.

Interdot coupling in a Si-based coupled double dot system for spin qubit gate

A Si-based coupled double dot has been studied for its application to two-qubit gate. The authors manipulated electron number of each dot by using its adjacent side gate and finally observed a honeycomb charge-stability pattern, demonstrating interdot capacitive coupling. From the honeycomb diagram the capacitance-related interdot coupling parameters were extracted. Moreover, a fine structure in a conductance trace near the triple point of the honeycomb, where the tunnel coupling is maximized, was measured for finite bias, and its dependence on the interdot coupling was attributed to the spin exchange between the two dots.

Integration of Novel Capacitor Structure for High Density FeRAM With Barrier Metal TiAlN and (Bi,La)4Ti3O12

16M 1T1C ferroelectric random access memory was successfully integrated by newly proposed scheme named Recessed Open Barrier (ROB) structure with planar Pt/BLT/Pt/IrOx/Ir stacked capacitor. In conventional barrier metal scheme which bottom electrode was stacked, oxygen diffused through the bottom electrode interface formed during MTP structure integration, and oxidized the edge of barrier metal resulting compressive stress. The failure was accelerated by free oxygen diffusion as the stress built up to make the bottom electrode pop-up. In this paper, the barrier metal TiAlN was recessed and refilled by ALD Al2O3 after bottom electrode patterning. By this novel structure, oxidation resistance was greatly improved, because oxygen diffusion path to BM was much longer than conventional scheme. The contact resistance of storage node was below 10 kΩ/plug after all the thermal budget relevant to BLT capacitor.

Crystallographic Orientation Dependent Ferroelectric Characteristics of (Bi3.3,La0.8)Ti3O12 (BLT) Capacitors

ABSTRACT The 70 nm thick (Bi3.3,La0.8)Ti3O12 (BLT) thin films were fabricated by deposition multiple spin coating layers and then crystallized by RTA and FA on Pt/TiOx/SiO2/Si substrate. Films were synthesized by MOD (metal organic decomposition) derived precursor to easy mass production. The randomly oriented BLT thin films have resulted from newly developed noble bake process, while a highly c-axis preferred orientation occurs for conventional baked thin film. The texture coefficient of I(004), I(117), I(111) and I(200) of noble baked BLT capacitors has 0, 0.24, 1.35 and 1.92, respectively. The films were very dense with no apparent pore site. The switching polarization (P*-P∧) and coercive voltage (2 Vc) of randomly oriented BLT thin films were nearly saturated at 3 V to have 20.03 μ C/cm2 and 1.38 V, respectively. However, strongly c-axis oriented thin films have 10.1 μ C/cm2 and 1.42 V for drive 3 V. The random orientation BLT shows good insulating behavior (9.4E-7 A/cm2 at 3 V). Both randomly oriented capacitor and highly c-axis preferred orientation thin films show no degradation of polarization due to fatigue after 1E11 cycles using 3 V (428.5 kV/cm) bipolar square pulse at 1 MHz.

Ferroelectric Properties and Current Conducition mechanisms of Pt/(Bi,La) 4 Ti 3 O 12 /Pt Capacitors

We studied the ferroelectric properties and current conduction characteristics of (Bi,La) 4 Ti 3 O 12 (BLT) thin films. Random oriented BLT thin films were prepared on Pt/IrO x /Ir structure by MOD (metal-organic decomposition), and crystallized by RTA (rapid thermal annealing) and the subsequent furnace annealing process. The swichable polarization polarization (P*-P) and coercive voltage (2Vc) of BLT thin films were 20.1 w C/cm 2 and 1.8V at 3V driving voltage. The leakage current density (J L ) with bias polarity was 4.0E-7 A/cm 2 under positive and 9.7E-7 A/cm 2 under negative, respectively. The leakage current characteristics of BLT films on Pt/IrO x /Ir electrode were controlled by the modified Schottky emission, because the field emission of BLT capacitors are quite dependent upon temperature and the measured data are well straightly fitted in log(J/E) vs E 1/2 plots. This result is shown to combine interface and bulk controlled conduction properties. The barrier height ( | B ) of the Pt/BLT/Pt was calculated as 0.53 eV by temperature-dependent current-voltage measurements.

Analysis of Si–SiO2 Interface Using Charge Pumping Method with Various Capping Materials between Gate Stacks and Inter Layer Dielectric in NAND Flash Memory

We report the dependence of Si–SiO2 interface trap density after Fowler–Nordheim (F/N) stress on various capping materials between gate stacks and an inter layer dielectric (ILD) in a NAND Flash memory cell. The interface trap density was characterized by charge pumping method (CPM). When the capping layer is an oxide, the Nit after F/N stress is approximately 2×1011 cm-2, which is about 50% smaller than that with a nitride layer. We found that the oxide layer causes compressive stress whereas the nitride layer causes a relatively high tensile stress in the underlying substrate by measuring the warp change of the substrate. To correlate the interface state density and data retention characteristics, we measured Vt shift after high-temperature baking. When an oxide capping layer is used, the retention characteristics of memory devices are greatly improved compared to the nitride capping case. These results show a good correlation between the interface characteristics and mechanical stress behaviors.

Grain Size and Orientation Control in Lead-Free (Bi,La)4Ti3O12 Thin Film Deposited by Spin-On Method for High Density FeRAM Device

A 16Mb 1T1C FeRAM device was successfully fabricated with the lead-free BLT capacitors. The average value of the switchable polarization obtained in the 32k-array (unit capacitor size: 0.68 μm2) BLT capacitors was about 16 μC/cm2 at the applied voltage of 3V and the uniformity within an 8-inch wafer was about 2.8%. But random bit failures were detected during the measuring the bit-line signal of each cell. It was revealed that the grain size and orientation of the BLT thin film were severely non-uniform. Therefore, the grain size and orientation was optimized by varying the process conditions of nucleation step. The random bit failure issue was solved by adopting the optimized BLT film. The cell signal margin of the optimized FeRAM device was about 340 mV.

Gate Annealing of Cycling Endurance and Interface States for Highly Reliable Flash Memory

We report on superior cycling endurance due to a low interface trap density, which accounts for the high gate annealing temperature in flash memory. The interface trap density was characterized using a charge pumping method (CPM). The cycling VTH shift in an erase state value of 1.35 V at 850 °C temperature of an annealing, as measured on a 90-nm-technology 1-Mbit cell array, selected randomly from 1 Gbit cells, drops to less than 0.9 V after annealing at 950 °C. These superior electrical properties resulted from a complete relaxation of silicon interface trap charges due to a plasma-induced attack during gate annealing at temperatures over 950 °C for a long time. Therefore, the key factor for highly reliable endurance with cycling is believed to be the interface trap control of the thermal annealing carried out after gate etching.